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IS27HC010-70PL Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS27HC010-70PL Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
1 / 11 page ISSI® IS27HC010 Integrated Silicon Solution, Inc. 1 EP009-1F 07/18/97 ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1997, Integrated Silicon Solution, Inc. FEATURES • Fast read access time: 30 ns • Pin compatible with the IS27C010 • High-speed write programming — Typically less than 30 seconds • Industrial and commercial temperature ranges available • ±10% power supply tolerance • JEDEC-approved pinout • Standard 32-pin DIP, PLCC, and TSOP packages DESCRIPTION The ISSI IS27HC010 is an ultra-high-speed 1 megabit (128K- word by 8-bit) Ultraviolet Erasable CMOS Programmable Read-Only Memory. It utilizes the standard JEDEC pinout making it functionally compatible with the IS27C010, but with significantly faster access capability. This superior random access capability results from a focused high-speed design. This offers users bipolar speeds with higher density, lower cost, and proven reliability. The device is ideal for use with the faster processors. Design- ers may take full advantage of high-speed digital signal processors and microprocessors by allowing code to be executed at full speed directly out of EPROM. Typical applica- tions include laser printers, switching networks, graphics, workstations, high-speed modems, and digital signal process- ing. The IS27HC010 uses ISSI's write programming algorithm which allows the entire chip to be programmed in typically less than 30 seconds. This product is available inOne-Time Programmable (OTP) PDIP, PLCC, and TSOP packages over commercial and industrial temperature ranges. IS27HC010 131,072 x 8 HIGH-SPEED CMOS EPROM ISSI® VCC GND VPP OE OUTPUT ENABLE CHIP ENABLE AND PROG LOGIC 1,048,576-BIT CELL MATRIX CE PGM OUTPUT BUFFERS Y GATING X DECODER Y DECODER 17 A0-A16 8 DQ0-DQ7 FUNCTIONAL BLOCK DIAGRAM JULY 1997 |
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