250ksps, +3V, 8-/4-Channel, 12-Bit ADCs

with +2.5V Reference and Parallel Interface

_______________________________________________________________________________________

5

Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have

been removed.

Note 3: Offset nulled.

Note 4: On channel is grounded; sine wave applied to off channels.

Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle.

Note 7: External load should not change during conversion for specified accuracy.

Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.

TIMING CHARACTERISTICS (continued)

20

70

ns

RD Rise to Output Disable

RD Fall to Output Data Valid

20

70

ns

RD Fall to INT High Delay

100

ns

CS Fall to Output Data Valid

110

ns

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

CONDITIONS

HBEN to Output Data Valid

20

110

ns

3k

Ω

3k

Ω

DOUT

DOUT

20pF

20pF

Figure 1. Load Circuits for Enable/Disable Times