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WCMA1008U1X-SF70 Datasheet(PDF) 1 Page - Weida Semiconductor, Inc. |
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WCMA1008U1X-SF70 Datasheet(HTML) 1 Page - Weida Semiconductor, Inc. |
1 / 12 page 128K x 8 Static RAM WCMA1008U1X A1008U1X Features •High Speed — 55ns and 70ns availability • Voltage range — 2.7V–3.6V • Ultra low active power — Typical active current: 20 mA @ f = fmax (70ns speed) • Low standby power • Easy memory expansion with CE and OE features • Automatic power-down when deselected • CMOS for optimum speed/power Functional Description The WCMA1008U1X is a high-performance CMOS static RAM organized as 128K words by 8 bits. Easy memory expan- sion is provided by an active LOW Chip Enable (CE1), an ac- tive HIGH Chip Enable (CE2), an active LOW Output Enable (OE) and three-state drivers. These devices have an automat- ic power-down feature, reducing the power consumption by over 99% when deselected. Writing to the device is accomplished by taking Chip Enable one (CE1) and Write Enable (WE) inputs LOW and the Chip Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip En- able one (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable two (CE2) HIGH. Under these conditions, the contents of the memory location speci- fied by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The WCMA1008U1X is available in a 32 Lead TSOP and STSOP packages. Logic Block Diagram A6 A7 A16 A14 A12 WE VCC A4 A13 A8 A9 OE STSOP Top View (not to scale) 30 28 29 31 24 19 23 22 21 20 18 13 17 16 15 14 11 12 I/O2 I/O1 GND I/O7 I/O4 I/O5 I/O6 I/O0 CE1 A11 A5 9 10 32 1 2 3 4 5 6 7 8 CE2 A15 NC A10 I/O3 A1 A0 A3 A2 26 25 26 27 A6 A7 A16 A14 A12 WE VCC A4 A13 A8 A9 OE TSOP I Top View (not to scale) 1 6 2 3 4 5 7 32 27 31 30 29 28 26 21 25 24 23 22 19 20 I/O2 I/O1 GND I/O7 I/O4 I/O5 I/O6 I/O0 CE1 A11 A5 17 18 8 9 10 11 12 13 14 15 16 CE2 A15 NC A10 I/O3 A1 A0 A3 A2 Pin Configurations A1 A2 A3 A4 A5 A6 A7 A8 COLUMN DECODER INPUT BUFFER POWER DOWN WE OE I/O0 CE2 I/O1 I/O2 I/O3 512x 256x 8 ARRAY I/O7 I/O6 I/O5 I/O4 A0 CE1 |
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