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WCMA1008U1X-TF55 Datasheet(PDF) 5 Page - Weida Semiconductor, Inc. |
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WCMA1008U1X-TF55 Datasheet(HTML) 5 Page - Weida Semiconductor, Inc. |
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5 / 12 page  WCMA1008U1X 5 Switching Characteristics Over the Operating Range[5] Parameter Description WCMA1008U1X-55 WCMA1008U1X-70 Unit Min. Max. Min. Max. READ CYCLE tRC Read Cycle Time 55 70 ns tAA Address to Data Valid 55 70 ns tOHA Data Hold from Address Change 5 10 ns tACE CE1 LOW and CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 20 35 ns tLZOE OE LOW to Low Z[6] 10 10 ns tHZOE OE HIGH to High Z[6, 7] 20 25 ns tLZCE CE1 LOW and CE2 HIGH to Low Z [6] 10 10 ns tHZCE CE1 HIGH or CE2 LOW to High Z [6, 7] 20 25 ns tPU CE1 LOW and CE2 HIGH to Power-Up 0 0 ns tPD CE1 HIGH or CE2 LOW to Power-Down 55 70 ns WRITE CYCLE[8,] tWC Write Cycle Time 55 70 ns tSCE CE1 LOW and CE2 HIGH to Write End 45 60 ns tAW Address Set-Up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 45 55 ns tSD Data Set-Up to Write End 25 30 ns tHD Data Hold from Write End 0 0 ns tHZWE WE LOW to High Z[6, 7] 20 25 ns tLZWE WE HIGH to Low Z[6] 5 5 ns Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 8. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. |
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