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WCSS0418V1F-117 Datasheet(PDF) 4 Page - Weida Semiconductor, Inc. |
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WCSS0418V1F-117 Datasheet(HTML) 4 Page - Weida Semiconductor, Inc. |
4 / 18 page WCSS0418V1F Document #: 38-05245 Rev. ** Page 4 of 18 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCDV) is 7.5 ns (117-MHz device). The WCSS0418V1F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The in- terleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advance- ment through the burst sequence is controlled by the ADV in- put. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchro- nous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank se- lection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all as- serted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deassert- ed during this first cycle). The address presented to the ad- dress inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are sat- isfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses pre- sented are loaded into the address register and the burst counter/control logic and delivered to the RAM core. The write inputs (GW, BWE, and BWS[1:0]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. Byte writes are allowed. During byte writes, BWS0 controls DQ[7:0] and DP0 while BWS1 controls DQ[15:8] and DP1. All I/Os are three-stated dur- ing a byte write. Since these are common I/O devices, the asynchronous OE input signal must be deasserted and the CE2 Input- Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 Input- Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. OE Input- Asynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. ZZ Input- Asynchronous Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power standby mode in which all other inputs are ignored, but the data in the memory array is maintained. Leaving ZZ floating or NC will default the device into an active state. ZZ pin has an internal pull-down. MODE - Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. When left floating or NC, defaults to interleaved burst order. Mode pin has an internal pull-up. DQ[15:0] I/O- Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[15:0] and DP[1:0] are placed in a three-state condition. The outputs are automatically three-stated when a WRITE cycle is detected. DP[1:0] I/O- Synchronous Bidirectional Data Parity lines. These behave identical to DQ[15:0] described above. These signals can be used as parity bits for bytes 0 and 1 respectively. VDD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply. VSS Ground Ground for the device. Should be connected to ground of the system. VDDQ I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.5 or 3.3V power supply. NC - No connects. DNU - Do not use pins. Should be left unconnected or tied LOW. Pin Descriptions (continued) Name I/O Description |
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