WCSS0418V1F

Document #: 38-05245 Rev. **

Page 4 of 18

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. Maximum access delay from

The WCSS0418V1F supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The in-

terleaved burst order supports Pentium and i486 processors.

The linear burst sequence is suited for processors that utilize

a linear burst sequence. The burst order is user selectable,

and is determined by sampling the MODE input. Accesses can

be initiated with either the Processor Address Strobe (ADSP)

or the Controller Address Strobe (ADSC). Address advance-

ment through the burst sequence is controlled by the ADV in-

put. A two-bit on-chip wraparound burst counter captures the

first address in a burst sequence and automatically increments

the address for the rest of the burst access.

Byte write operations are qualified with the Byte Write Enable

Enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip synchro-

nous self-timed write circuitry.

asynchronous Output Enable (OE) provide for easy bank se-

is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions

serted active, and (2) ADSP or ADSC is asserted LOW (if the

access is initiated by ADSC, the write inputs must be deassert-

ed during this first cycle). The address presented to the ad-

dress inputs is latched into the address register and the burst

counter/control logic and presented to the memory core. If the

OE input is asserted LOW, the requested data will be available

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are sat-

active, and (2) ADSP is asserted LOW. The addresses pre-

sented are loaded into the address register and the burst

counter/control logic and delivered to the RAM core. The write

clock cycle. If the write inputs are asserted active (see Write

Cycle Descriptions table for appropriate states that indicate a

write) on the next clock rise, the appropriate data will be

latched and written into the device. Byte writes are allowed.

ing a byte write. Since these are common I/O devices, the

asynchronous OE input signal must be deasserted and the

Input-

Synchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with

Input-

Synchronous

OE

Input-

Asynchronous

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,

the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input

data pins.

ZZ

Input-

Asynchronous

Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power standby

mode in which all other inputs are ignored, but the data in the memory array is maintained. Leaving

ZZ floating or NC will default the device into an active state. ZZ pin has an internal pull-down.

MODE

-

Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.

Pulled LOW selects the linear burst order. When left floating or NC, defaults to interleaved burst

order. Mode pin has an internal pull-up.

I/O-

Synchronous

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by

the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified

OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as

automatically three-stated when a WRITE cycle is detected.

I/O-

Synchronous

can be used as parity bits for bytes 0 and 1 respectively.

Power Supply

Power supply inputs to the core of the device. Should be connected to 3.3V power supply.

Ground

Ground for the device. Should be connected to ground of the system.

I/O Power

Supply

Power supply for the I/O circuitry. Should be connected to a 2.5 or 3.3V power supply.

NC

-

No connects.

DNU

-

Do not use pins. Should be left unconnected or tied LOW.

Name

I/O

Description