WCSN0436V1P-100AC datasheet(10/14 Pages) WEIDA

Part #	WCSN0436V1P-100AC

Description	128Kx36 Pipelined SRAM with NoBL TM Architecture

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Manufacturer	WEIDA [Weida Semiconductor, Inc.]

Direct Link	http://www.weida.com.my/website/

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10 / 14 page

WCSN0436V1P

Document #: 38-05246 Rev. **

Page 10 of 14

Switching Waveforms

CEN

CLK

ADDRESS

CE

WE &

Data-

In/Out

tCYC

tCH tCL

RA1

tAH

tAS

tWS tWH

tCES tCEH

tCO

Q4

Q1

= DON’T CARE

= UNDEFINED

The combination of WE & BWS[3:0] define a write cycle (see Write Cycle Description table).

Out

D2

In

D5

In

Out

WA2

RA3

RA4

WA5

RA6

RA7

tCLZ

tDOH

Q3

Out

tCHZ

CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select

the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for

Device

originally

deselected

Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW.

Q7

Out

tCHZ

tCENS

tCENH

tDOH

BWS[3:0]

READ/WRITE/DESELECT Sequence

CEN HIGH blocks

Q6

Out

all synchronous inputs

tDS

tDH

OE held LOW.

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