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WCSS0418V1F-100AI Datasheet(PDF) 9 Page - Weida Semiconductor, Inc. |
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WCSS0418V1F-100AI Datasheet(HTML) 9 Page - Weida Semiconductor, Inc. |
9 / 18 page WCSS0418V1F Document #: 38-05245 Rev. ** Page 9 of 18 Switching Characteristics Over the Operating Range[10] Parameter Description -117 -100 Min. Max. Min. Max. Unit tCYC Clock Cycle Time 8.5 10 ns tCH Clock HIGH 3.0 4.0 ns tCL Clock LOW 3.0 4.0 ns tAS Address Set-Up Before CLK Rise 2.0 2.0 ns tAH Address Hold After CLK Rise 0.5 0.5 ns tCDV Data Output Valid After CLK Rise 7.5 8.0 ns tDOH Data Output Hold After CLK Rise 2.0 2.0 ns tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.0 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 ns tWES BWS[1:0], GW, BWE Set-Up Before CLK Rise 2.0 2.0 ns tWEH BWS[1:0], GW, BWE Hold After CLK Rise 0.5 0.5 ns tADVS ADV Set-Up Before CLK Rise 2.0 2.0 ns tADVH ADV Hold After CLK Rise 0.5 0.5 ns tDS Data Input Set-Up Before CLK Rise 2.0 2.0 ns tDH Data Input Hold After CLK Rise 0.5 0.5 ns tCES Chip Enable Set-Up 2.0 2.0 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 ns tCHZ Clock to High-Z[11, 12] 3.5 3.5 ns tCLZ Clock to Low-Z[11, 12] 00 ns tEOHZ OE HIGH to Output High-Z[11, 13] 3.5 3.5 ns tEOLZ OE LOW to Output Low-Z[11, 13] 00 ns tEOV OE LOW to Output Valid 3.5 3.5 ns Notes: 10. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads. 11. tCHZ, tCLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 12. At any given voltage and temperature, tCHZ (max.) is less than tCLZ (min.). 13. This parameter is sampled and not 100% tested. |
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