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STM8S001J3 Datasheet(PDF) 49 Page - STMicroelectronics |
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STM8S001J3 Datasheet(HTML) 49 Page - STMicroelectronics |
49 / 84 page DS12129 Rev 4 49/84 STM8S001J3 Electrical characteristics 74 Total current consumption and timing in forced reset state Current consumption of on-chip peripherals Subject to general operating conditions for VDD and TA. HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V. Table 28. Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max(1) Unit IDD(R) Supply current in reset state (2) VDD = 5 V 400 - µA VDD = 3.3 V 300 - tRESETBL Reset release to vector fetch - - 150 µs 1. Guaranteed by design. 2. Characterized with all I/Os tied to VSS. Table 29. Peripheral current consumption Symbol Parameter Typ. Unit IDD(TIM1) TIM1 supply current (1) 1. Data based on a differential IDD measurement between reset configuration and timer counter running at 16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production. 210 µA IDD(TIM2) TIM2 supply current (1) 130 IDD(TIM4) TIM4 timer supply current (1) 50 IDD(UART1) UART1 supply current(1) 120 IDD(SPI) SPI supply current(1) 45 IDD(I2C) I2C supply current (1) 65 IDD(ADC1) ADC1 supply current when converting(1) 1000 |
Similar Part No. - STM8S001J3_V01 |
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Similar Description - STM8S001J3_V01 |
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