HDMP-0482 datasheet(9/12 Pages) HP

Part #	HDMP-0482

Description	Octal Cell Port Bypass Circuit with CDR and Data Valid Detection

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Manufacturer	HP [Agilent(Hewlett-Packard)]

Direct Link	http://www.home.agilent.com

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9

Figure 5. Eye Diagram of TO_NODE[1]

± High Speed Differential Output.

Note: Measurement taken with a 27-1 PRBS input to FM_NODE[0]

±.

Figure 6. Setup for Measurement of Random Jitter.

Figure 7. Setup for Measurement of Deterministic Jitter.

HDMP-0482

+/- FM_NODE[0]

+/- TO_NODE[0]

Ch 1/2

2

106.25 MHz

HP 70311A

Clock Source

K28.7

HP70841B

Pattern Generator

+/- Data

Clock

1062.5 MHz

Trigger

HP 83480A

Digital

Communication

Analyzer

1/10

106.25 MHz

1.4V

Bias Tee

2

BYPASS[0]-

N/C

1 K

Ω

BYPASS[1:4]-

REFCLK

HDMP-0482

+/- FM_NODE[0]

+/- TO_NODE[0]

Ch 1/2

2

53.125 MHz

106.25 MHz

HP 70311A

Clock Source

-K28.5

+K28.5

HP70841B

Pattern Generator

+/- Data

Clock

1062.5 MHz

Trigger

HP 83480A

Digital

Communication

Analyzer

1/10

106.25 MHz

1.4V

Bias Tee

2

BYPASS[0]-

N/C

1 K

Ω

BYPASS[1:4]-

REFCLK

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HDMP-0482 Datasheet(PDF) 9 Page - Agilent(Hewlett-Packard)

HDMP-0482 Datasheet(HTML) 9 Page - Agilent(Hewlett-Packard)

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