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SP9502JS Datasheet(PDF) 4 Page - Sipex Corporation |
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SP9502JS Datasheet(HTML) 4 Page - Sipex Corporation |
4 / 11 page SP9502DS/02 SP9502 Dual, 12-Bit, Voltage Output D/A Converter © Copyright 1999 Sipex Corporation 4 are forced to 1000 0000 0000 and the DAC outputs will settle to OV. Active low. Pin 13 — WR1 — Write Input1 — In conjunction with CS (pin 14), enables input register selection, and controls the transfer of data from the input bus to the input registers. Active low. Pin 14 — CS — Chip Select — Enables writing data to input registers and/or transferring data from input bus to DAC registers. Pin 15 — V OUT1 — Voltage Output from DAC1. Pin 16 — DB 11 — Data Bit 11; most significant bit. Pin 17 — DB 10 — Data Bit 10. Pin 18 — DB 9 — Data Bit 9. Pin 19 — DB 8 — Data Bit 8. Pin 20 — DB 7 — Data Bit 7. Pin 21 — DB 6 — Data Bit 6. Pin 22 — DB 5 — Data Bit 5. Pin 23 — DB 4 — Data Bit 4. Pin 24 — DB 3 — Data Bit 3. Pin 25 — DB 2 — Data Bit 2. Pin 26 — DB 1 — Data Bit 1. Pin 27 — DB 0 — Data Bit 0; LSB Pin 28 — N.C. — No Connection. PINOUT — 28–PIN SOIC & DIP PIN ASSIGNMENTS Pin 1 — N.C. — No Connection. Pin 2 — V OUT 2 — Voltage Output from DAC2. Pin 3 — V SS — –5V Power Supply Input. Pin 4 — V DD — +5V Power Supply Input. Pin 5 — CLR — Clear. Gated with WR2 (pin 12). Active low. Clears both DAC outputs to 0V. Pin 6 — REF IN2 — Reference Input for DAC2. Pin 7 — GND — Ground. Pin 8 — B1/B2 — Byte 1/Byte 2 — Selects Data Input Format. A logic “1” on pin 8 selects the 12– bit mode, and all 12 data bits are presented to the DAC(s) unchanged; a logic “0” selects the 8–bit mode, and the four LSBs are connected to the four MSBs, allowing an 8–bit MSB–justified interface. Pin 9 — A — Address for DAC Selection — A logic “0” selects DAC 1; a logic “1” selects DAC 2. Pin 10 — REF IN1 — Reference Input for DAC1. Pin 11 — XFER — Transfer. Gated with WR2 (pin 12); loads all DAC registers simultaneously. Active low. Pin 12 — WR2 — Write Input 2 — In conjunction with XFER (pin 11), controls the transfer of data from the input registers to the DAC registers. In conjunction with CLR (pin 5), the DAC registers N.C. VOUT2 VSS VDD CLR Ref In 2 GND B1/B2 A Ref In 1 XFER WR2 WR1 CS N.C. DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 VOUT1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 SP9502 |
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