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SP9502JS Datasheet(PDF) 5 Page - Sipex Corporation |
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SP9502JS Datasheet(HTML) 5 Page - Sipex Corporation |
5 / 11 page SP9502DS/02 SP9502 Dual, 12-Bit, Voltage Output D/A Converter © Copyright 1999 Sipex Corporation 5 most significant bits (MSBs), allowing an 8-bit MSB-justified interface. All data inputs are enabled using the CS signal in both modes. The digital inputs are designed to be both TTL and 5V CMOS compatible. In order to reduce the DAC full scale output sensitivity to the large weighting of the MSB’s found in conventional R-2R resistor ladders, the 3 MSB’s are decoded into 8 equally weighted levels. This reduces the contribution of each bit by a factor of 4, thus, reducing the output sensitivity to mis- matches in resistors and switches by the same amount. Linearity errors and stability are both improved for the same reasons. Each D/A con- verter is separated from the data bus by two reg- isters, each consisting of level-triggered latches, Figure 1. The first register (input register) is 12- bits wide. The input register is selected by the address input A 0 and A1 and is enabled by the CS and WR1 signals. In the 8-bit mode, the enable signal to the 8 MSB’s is disabled by a logic low on B1/B2 to allow the 4 LSB’s to be updated. The second register (DAC register), accepts the de- coded 3 MSB’s plus the 9 LSB’s. The two DAC registers are updated simultaneously for both DAC’s using the XFER and WR2 signals. Using the CLR and WR2 signals or the power-on-reset, (enabled when the power is switched on) the DAC registers are set to 1000 0000 0000 and the DAC outputs will settle to 0V. Using the control logic inputs, the user has full control of address decoding, chip enable, data transfer and clearing of the DAC’s. The control logic inputs are level triggered, and like the data inputs, are TTL and CMOS compatible. The truth table (Table 2) shows the appropriate functions associated with the states of the control logic inputs. The DACs themselves are implemented with a precision thin–film resistor network and CMOS transmission gate switches. Each D/A converter is used to convert the 12-bit input from its DAC register to a precision voltage. The bipolar voltage output of the SP9502 is created on-chip from the DAC Voltage Output (V DAC) by using an operational amplifier and two feedback resistors connected as shown in Figure 2. This configuration produces a ±4.5V bipolar output rangewithstandardoffsetbinarycoding.(SeeTable1) THEORY OF OPERATION TheSP9502consistsoffivemainfunctionalblocks — input data multiplexer, data registers, control logic,12-bit D/A converters, and two bipolar output voltage amplifiers. The input data multi- plexer is designed to interface to either 12- or 8-bit microprocessor data busses. The input data format is controlled by the B1/B2 signal — a logic “1” selects the 12-bit mode, while a logic “0” selects the 8-bit mode. In the 12-bit mode the data is transferred to the input registers without changes in its format. In the 8-bit mode, the four least significant bits (LSBs) are connected to the four FEATURES The SP9502 is a low power, dual version of the popular SP9345, Quad 12-Bit Digital-to-Analog Converter. This Dual, Voltage Output, 12-Bit Digital-to-Analog Converter features ±4.5V output swings when using ±5 volt supplies. The input coding format used is standard offset binary. (Refer to Table 1 below.) The converter utilizes double-buffering on each of the12 parallel digital inputs, for easy microprocessor interface. Each 12-bit DAC is independently addressable and both DACS may be simulta- neously updated using a single XFER command. The output settling-time is specified at 4 µs to full 12–bit accuracy when driving a 5Kohm,50pf load combination. The SP9502, Dual 12-Bit Digital- to-Analog Converter is ideally suited for applica- tions such as ATE, process controllers, robotics, and instrumentation. The SP9502 is available in 28–pin plastic SOIC and plastic DIP packages, specified over the commercial (0 °C to +70°C) temperature range. Table 1. Offset Binary Coding INPUT OUTPUT MSB LSB 1111 1111 1111 VREF - 1 LSB 1111 1111 1110 VREF - 2 LSB 1000 0000 0001 0 + 1 LSB 1000 0000 0000 0 0000 0000 0001 -VREF + 1 LSB 0000 0000 0000 -VREF 1 LSB = 2VREF 212 |
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