 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DP8522AV-25 Datasheet(PDF) 9 Page - National Semiconductor (TI) |
|
|
||||||||||||||||||||||||||||||
DP8522AV-25 Datasheet(HTML) 9 Page - National Semiconductor (TI) |
|
|
9 / 70 page  20 Signal Descriptions (Continued) Pin Device (If not Input Description Name applicable to all) Output 26 COMMON DUAL PORT SIGNALS GRANTB DP8522A O GRANT B This output indicates which port is currently granted access to the VRAM array When GRANTB is asserted Port B has access to the array When only GRANTB is negated Port A has access to the VRAM array This signal is used to multiplex the signals R0 – 8 9 10 C0 – 8 9 10 B0 – 1 WIN LOCK and ECAS0–1 to the DP8522A when using dual accessing LOCK DP8522A I LOCK This input can be used by the currently granted port to ‘‘lock out’’ the other port from the VRAM array by inserting wait states into the locked out port’s only access cycle until LOCK is negated 27 VRAM TRANSFER CYCLE SIGNALS AVSRLRQ I ADVANCED VIDEO SHIFT REGISTER LOAD REQUEST This must precede the VSRL input going low by the amount of time necessary to guarantee that any currently executing access and pending refresh can finish This input disables Port B and refresh requests until four CLK periods after VSRL has transitioned low This input may be held low until the video RAM transfer cycle is completed or may be momentarily pulsed low VSRL I VIDEO SHIFT REGISTER LOAD This input causes the DT OE output to transition low immediately Therefore when executing a video RAM shift register load VSRL transitions low before RAS goes low The DT OE output will transition high from VSRL going high or four CLK periods (rising clock edges) from VSRL going low whichever occurs first VSRL low also disables the WIN input from affecting the DT OE logic until the video shift register load access is over 28 POWER SIGNALS AND CAPACITOR INPUT VCC I POWER Supply Voltage GND I GROUND Supply Voltage Reference CAP I CAPACITOR This input is used by the internal PLL for stabilization The value of the ceramic capacitor should be 01 mF and should be connected between this input and ground 29 CLOCK INPUTS There are two clock inputs to the DP8520A21A22A CLK and DELCLK These two clocks may both be tied to the same clock input or they may be two separate clocks running at different frequencies asynchronous to each other CLK I SYSTEM CLOCK This input may be in the range of 0 Hz up to 25 MHz This input is generally a constant frequency but it may be controlled externally to change frequencies or perhaps be stopped for some arbitrary period of time This input provides the clock to the internal state machine that arbitrates between accesses and refreshes This clock’s positive edges and negative levels are used to extend the WAIT (DTACK) signals Ths clock is also used as the reference for the RAS precharge time and RAS low time during refresh All Port A and Port B accesses are assumed to be synchronous to the system clock CLK DELCLK I DELAY LINE CLOCK The clock input DELCLK may be in the range of 6 MHz to 20 MHz and should be a multiple of 2 (ie 6 8 10 12 14 16 18 20 MHz) to have the DP8520A21A22A switching characteristics hold If DELCLK is not one of the above frequencies the accuracy of the internal delay line will suffer This is because the phase locked loop that generates the delay line assumes an input clock frequency of a multiple of 2 MHz For example if the DELCLK input is at 7 MHz and we choose a divide by 3 (program bits C0 – 2) this will produce 2333 MHz which is 16667% off of 2 MHz Therefore the DP8520A21A22A delay line would produce delays that are shorter (faster delays) than what is intended If divide by 4 was chosen the delay line would be longer (slower delays) than intended (175 MHz instead of 2 MHz) (See Section 10 for more information) This clock is also divided to create the internal refresh clock 9 |
Similar Part No. - DP8522AV-25 |
|
Similar Description - DP8522AV-25 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
