 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DP8520AV-25 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
|
|
||||||||||||||||||||||||||||||
DP8520AV-25 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
|
|
7 / 70 page  20 Signal Descriptions Pin Device (If not Input Description Name applicable to all) Output 21 ADDRESS RW AND PROGRAMMING SIGNALS R0 – 10 DP8522A I ROW ADDRESS These inputs are used to specify the row address during an access or refresh to the VRAM or for a VRAM transfer cycle They are also used R0 – 9 DP8520A21A I to program the chip when ML is asserted (except R10) C0 – 10 DP8522A I COLUMN ADDRESS These inputs are used to specify the column address during an access to the VRAM or for a VRAM transfer cycle They are also used C0 – 9 DP8520A21A I to program the chip when ML is asserted (except C10) B0 B1 I BANK SELECT Depending on programming these inputs are used to select a group of RAS and CAS outputs to assert during an access They are also used to program the chip when ML is asserted ECAS0–1 I ENABLE CAS These inputs are used to enable a single or group of CAS outputs when asserted In combination with the B0 B1 and the programming bits these inputs select which CAS output or CAS outputs will assert during an access ECAS0 must be asserted for either CAS0orCAS1 to assert during an access ECAS1 must be asserted for either CAS2orCAS3 to assert during an access The ECAS signals can also be used to toggle a group of CAS outputs for pagenibble mode accesses They also can be used for byte write operations If ECAS0 is negated during programming continuing to assert the ECAS0 while negating AREQ or AREQB during an access will cause the CAS outputs to be extended while the RAS outputs are negated (the ECASn inputs have no effect during scrubbing refreshes) WIN I WRITE ENABLE IN This input is used to signify a write operation to the VRAM This input asserted will also cause CAS to delay to the next positive clock edge if address bit C9 is asserted during programming COLINC I COLUMN INCREMENT When the address latches are used and a refresh is not in progress this input functions as COLINC Asserting this signal causes the (EXTNDRF) I column address to be incremented by one When a refresh is in progress this signal when asserted is used to extend the refresh cycle by any number of periods of CLK until it is negated ML I MODE LOAD This input signal when low enables the internal programming register that stores the programming information 22 VRAM CONTROL SIGNALS Q0 – 10 DP8522A O VRAM ADDRESS These outputs are the multiplexed output of the R0 – 9 10 and C0 – 9 10 and form the VRAM address bus These outputs contain the Q0 – 9 DP8521A O refresh address whenever a refresh is in progress They contain high capacitive Q0 – 8 DP8521A O drivers with 20X series damping resistors RAS0–3 O ROW ADDRESS STROBES These outputs are asserted to latch the row address contained on the outputs Q0 – 8 9 10 into the VRAM When a refresh is in progress the RAS outputs are used to latch the refresh row address contained on the Q0 – 8 9 10 outputs in the VRAM These outputs contain high capacitive drivers with 20X series damping resistors CAS0–3 O COLUMN ADDRESS STROBES These outputs are asserted to latch the column address contained on the outputs Q0 – 8 9 10 into the VRAM These outputs have high capacitive drivers with 20X series damping resistors DT OE O DATA TRANSFEROUTPUT ENABLE This output transitions low before RAS goes low and transitions high before RAS goes high during a video RAM shift register load operation (see VSRL pin description) During normal write accesses this output is held high and for read accesses this output is asserted after CAS is asserted and is negated after CAS negates 7 |
Similar Part No. - DP8520AV-25 |
|
Similar Description - DP8520AV-25 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
