Publication Release Date: Oct 2000

- 7 -

Revision A5

Interrupt Vector Allocation

The W523Sxx provides a total of 4 trigger inputs to communicate with the outside world. Each trigger

pin can invoke 2 dedicate interrupt vectors depending on TG pins’ status (rising or falling). The table

below shows the relationship between triggers’ status and interrupt vectors.

INTERRUPT VECTOR

TRIGGER SOURCE

0

TG1F

1

TG2F

8

TG5F

9

TG6F

INTERRUPT VECTOR

TRIGGER SOURCE

4

TG1R

5

TG2R

12

TG5R

13

TG6R

32

POI

CPU Interface

The W523Sxx can communicate with an external microprocessor through a simple serial CPU

interface. The CPU interface consists of TG1, TG2 and STPA/BUSY pins, which are shown below:

Debounced OK. to clear the internal CPU

counter for preventing the system from

running away. (TG1F should be disabled.)

END

TG1

(Data)

TG2

(Clock)

STPA/Busy

AUD/SPK+

Note:

µS.

3. The "Clock" frequency of the TG2 pin can be set in the range: 10 KHz

- 1 MHz.

Busy signal will output "high" after the end of transmission. The rising timing of Busy signal is