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TMS320F2801ZGMA Datasheet(PDF) 11 Page - Texas Instruments |
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TMS320F2801ZGMA Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 134 page  www.ti.com 1 F280x, C280x, UCD9501 DSPs 1.1 Features TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, UCD9501 TMS320C2802, TMS320C2801 Digital Signal Processors SPRS230G – OCTOBER 2003 – REVISED FEBRUARY 2006 – Up to Six 32-bit/Six 16-bit Timers • High-Performance Static CMOS Technology • Three 32-Bit CPU Timers – 100 MHz (10-ns Cycle Time) • Serial Port Peripherals – Low-Power (1.8-V Core, 3.3-V I/O) Design – Up to 4 Serial Peripheral Interface (SPI) – 3.3-V Flash Voltage Modules • JTAG Boundary Scan Support – Up to 2 Serial Communications Interface • High-Performance 32-Bit CPU (TMS320C28x) (SCI), Standard UART Modules – 16 x 16 and 32 x 32 MAC Operations – Up to 2 CAN Modules – 16 x 16 Dual MAC – One Inter-Integrated-Circuit (I2C) Bus – Harvard Bus Architecture • 12-Bit ADC, 16 Channels – Atomic Operations – 2 x 8 Channel Input Multiplexer – Fast Interrupt Response and Processing – Two Sample-and-Hold – Unified Memory Programming Model – Single/Simultaneous Conversions – Code-Efficient (in C/C++ and Assembly) – Fast Conversion Rate: 160 ns/6.25 MSPS • On-Chip Memory (12.5 MSPS on F2809) – F2809: 128K X 16 Flash, 18K X 16 SARAM – Internal or External Reference F2808: 64K X 16 Flash, 18K X 16 SARAM • Up to 35 Individually Programmable, F2806: 32K X 16 Flash, 10K X 16 SARAM Multiplexed General-Purpose Input/Output F2802: 32K X 16 Flash, 6K X 16 SARAM (GPIO) Pins With Input Filtering F2801: 16K X 16 Flash, 6K X 16 SARAM 9501: 16K X 16 Flash, 6K X 16 SARAM • Advanced Emulation Features – C2802: 32K X 16 ROM, 6K X 16 SARAM – Analysis and Breakpoint Functions C2801: 16K X 16 ROM, 6K X 16 SARAM – Real-Time Debug via Hardware – 1K x 16 OTP ROM (F280x Only) • Development Tools Include • Boot ROM (4K x 16) – ANSI C/C++ Compiler/Assembler/Linker – With Software Boot Modes (via SCI, SPI, – Supports TMS320C24x™/240x Instructions CAN, I2C, and Parallel I/O) – Code Composer Studio™ IDE – Standard Math Tables – DSP/BIOS™ • Clock and System Control – JTAG Scan Controllers(1) – Dynamic PLL Ratio Changes Supported [Texas Instruments (TI) or Third-Party] – On-Chip Oscillator – Evaluation Modules – Clock-Fail-Detect Mode – Broad Third-Party Digital Motor Control – Watchdog Timer Module Support • Any GPIO A Pin Can Be Connected to One of • Low-Power Modes and Power Savings the Three External Core Interrupts – IDLE, STANDBY, HALT Modes Supported – Disable Individual Peripheral Clocks • Peripheral Interrupt Expansion (PIE) Block That Supports All 43 Peripheral Interrupts • Package Options • 128-Bit Security Key/Lock – Thin Quad Flatpack (PZ) – Protects Flash/OTP/L0/L1 Blocks – MicroStar BGA™ (GGM, ZGM) – Prevents Firmware Reverse Engineering • Temperature Options: • Enhanced Control Peripherals – A: -40°C to 85°C (PZ, GGM, ZGM) – Up to 16 PWM Outputs – S: -40°C to 125°C (PZ, GGM, ZGM) – Up to 4 HRPWM Outputs With 150 ps MEP – Q: -40°C to 125°C (PZ) Resolution (6 HRPWM Outputs on F2809) – Up to Four Capture Inputs – Up to Two Quadrature Encoder Interfaces (1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. UNLESS OTHERWISE NOTED this document contains Copyright © 2003–2006, Texas Instruments Incorporated PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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