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SMH4814NR03 Datasheet(PDF) 4 Page - Summit Microelectronics, Inc. |
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SMH4814NR03 Datasheet(HTML) 4 Page - Summit Microelectronics, Inc. |
4 / 44 page SMH4814 Preliminary Information Summit Microelectronics, Inc 2080 2.0 07/21/05 4 PIN DESCRIPTION Pin No. QFN Pin Type Name Description 1,2 I PD0, PD1 The PD pins are active high, logic level inputs. Protection diodes allow them to be overdriven when used in conjunction with a series limiting resistor. The PD pins have an internal pull-down current sink of 10uA typical. 3 I RESET# The RESET# pin is used to clear latched fault conditions. When this pin is asserted, the VGATEX and PUPX outputs are immediately disabled. Refer to the section on Circuit Breaker Operation for more information. The RESET# pin has an internal pull-up current source to 5V_CAP of 10uA typical. 4 I SCL SCL is the serial clock input. 5 I/O SDA SDA is the bidirectional serial data I/O port. 6, 7, 8, 9 O PUPA, PUPB, PUPC, PUPD The PUPX outputs are programmable active high/low open drain converter enable pins. They can be used in one of 4 programmable sequence positions to switch a load or enable a DC/DC converter after a programmable delay, tPGDn. The voltage on these pins cannot exceed 12V relative to VSS. 10 O FAULT# FAULT# is an open-drain, active-low output that indicates the fault status of the device. The device’s Status Register may be polled to determine more detailed information about the fault condition. 11 PWR VSS This is connected to the negative side of the supply. 12 I CBSENSE The circuit breaker sense input is used to detect over-current conditions across an external, low value sense resistor (RS) tied in series with the Power MOSFET. A voltage drop of greater than VCB (programmable level) across the resistor for longer than tCBD trips the circuit breaker. A programmable Quick-Trip™ sense point is also available. 13 I UV The UV pin is used as an under-voltage supply monitor, typically in conjunction with an external resistor ladder. VGATE_HS is enabled when the UV input > Vuv and disabled when UV < Vuv-Vuvhys. An optional programmable filter delay is also available on the UV input. 14 I OV The OV pin is used as an over-voltage supply monitor, typically in conjunction with an external resistor ladder. VGATE_HS is disabled when OV > Vov and enabled when OV < Vov-Vovhys. A filter delay is also available on the OV input. 15 I EN/TS The Enable/Temperature Sense input is the master enable input. If EN/TS is less than 2.5V, all VGATE outputs are disabled. 16 I SLEW_CNTL A capacitor connected to this pin controls the VGATE_HS Slew Rate. 17 I FEEDB Connect to the -48V 'B' feed using a series 100k resistor. The voltage on this pin is compared with the voltage on the FEEDA pin internally by the supply arbitration logic to determine which voltage will be used. |
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