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IDT709079L9PFI Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT709079L9PFI Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 17 page  6.42 IDT709079S/L Preliminary High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 9 Timing Waveform of a Bank Select Pipelined Read(1,2) tSC tHC CE0(B1) ADDRESS(B1) A0 A1 A2 A3 A4 A5 tSA tHA CLK 3495 drw 08 Q0 Q1 Q3 DATAOUT(B1) tCH2 tCL2 tCYC2 (3) ADDRESS(B2) A0 A1 A2 A3 A4 A5 tSA tHA CE0(B2) DATAOUT(B2) Q2 Q4 tCD2 tCD2 tCKHZ tCD2 tCKLZ tDC tCKHZ tCD2 tCKLZ (3) (3) tSC tHC (3) tCKHZ (3) tCKLZ (3) tCD2 A6 A6 tDC tSC tHC tSC tHC NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709079 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. Timing Waveform of a Bank Select Flow-Through Read(6) tSC tHC CE0(B1) ADDRESS(B1) A0 A1 A2 A3 A4 A5 tSA tHA CLK 3495 drw 08a D0 D3 tCD1 tCKLZ tCKHZ (1) (1) D1 DATAOUT(B1) tCH1 tCL1 tCYC1 (1) ADDRESS(B2) A0 A1 A2 A3 A4 A5 tSA tHA CE0(B2) DATAOUT(B2) D2 D4 tCD1 tCD1 tCKHZ tDC tCD1 tCKLZ tSC tHC (1) tCKHZ (1) tCKLZ (1) tCD1 A6 A6 tDC tSC tHC tSC tHC D5 tCD1 tCKLZ (1) tCKHZ (1) |
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