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IDT709079L12PFI Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT709079L12PFI Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 17 page 6.42 IDT709079S/L Preliminary High-Speed 32K x 8 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 10 Timing Waveform of a Left Port Write Flow-Through Right Port Read(1,2,3,4) DATAIN "A" CLK "B" R/ W "B" ADDRESS "A" R/ W "A" CLK "A" ADDRESS "B" NO MATCH MATCH NO MATCH MATCH VALID tCWDD tCD1 tDC DATAOUT "B" 3495 drw 09 VALID VALID tSW tHW tSA tHA tSD tHD tHW tCD1 tCCS tDC tSA tSW tHA (5) (5) NOTES: 1. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 2. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 4. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 5. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. |
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