IC61LV25616

2

Integrated Circuit Solution Inc.

AHSR022-0A

09/11/2001

FEATURES

• High-speed access time: 8, 10, 12, and 15 ns

• CMOS low power operation

• TTL compatible interface levels

• Single 3.3V

± 10% power supply

• Fully static operation: no clock or refresh

required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

256K x 16 HIGH SPEED ASYNCHRONOUS

CMOS STATIC RAM WITH 3.3V SUPPLY

DESCRIPTION

The

RAM organized as 262,144 words by 16 bits. It is fabricated

using

reliable process coupled with innovative circuit design

techniques, yields high-performance and low power consump-

tion devices.

When

CE is HIGH (deselected), the device assumes a standby

mode at which the power dissipation can be reduced down with

CMOS input levels.

Easy memory expansion is provided by using Chip Enable and

Output Enable inputs,

CE and OE. The active LOW Write

Enable (

WE) controls both writing and reading of the memory.

A data byte allows Upper Byte (

UB) and Lower Byte (LB)

access.

The IC61LV25616 is packaged in the JEDEC standard

44-pin 400mil SOJ, 44 pin 400mil TSOP-2 and 48-pin 6*8 TF-

BGA.

FUNCTIONAL BLOCK DIAGRAM

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

A0-A17

CE

OE

WE

256K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VCC

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB