6.42

IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with

ZBT

™

™

™

™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

7

NOTES:

2. When ADV/

LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of

the burst cycle (Read or Write) is determined by the status of the R/

W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (

tri-state two cycles after deselect is initiated.

4. When

CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/

Os remains unchanged.

5. To select the chip requires

6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

7. Q - Data read from the device, D - data written to the device.

NOTES:

2. Multiple bytes may be selected during the same cycle.

3. N/A for X18 configuration.

CEN

R/

W

Enable

ADV/

LD

BWx

ADDRESS

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

(2 cycles later)

L

L

Select

L

Valid

External

X

LOAD WRITE

L

H

Select

L

X

External

X

LOAD READ

L

X

X

H

Valid

Internal

LOAD WRITE /

BURST WRITE

BURST WRITE

L

X

X

H

X

Internal

LOAD READ /

BURST READ

BURST READ

L

X

Deselect

L

X

X

X

HiZ

L

X

X

H

X

X

DESELECT / NOOP

NOOP

HiZ

H

X

X

X

X

X

X

Previous Value

5296 tbl 08

OPERATION

R/

W

READ

H

XXX

X

WRITE ALL BYTES

L

L

L

L

L

LL

H

H

H

LH

LH

H

NO WRITE

L

HH

HH

5296 tbl 09