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IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with

ZBT

™

™

™

™

™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs

Commercial and Industrial Temperature Ranges

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol

Pin Function

I/O

Active

Description

Address Inputs

I

N/A

Synchronous Address inputs. The address register is triggered by a combination of the rising

edge of CLK, ADV/

LD low, CEN low, and true chip enables.

ADV/

LD

Advance / Load

I

N/A

ADV/

LD is a synchronous input that is used to load the internal registers with new address and

control when it is sampled low at the rising edge of clock with the chip selected. When

ADV/

LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is

sampled high then the internal burst counter is advanced for any burst that was in progress.

The external addresses are ignored when ADV/

LD is sampled high.

R/W

Read / Write

I

N/A

R/W signal is a synchronous input that identifies whether the c urrent load cycle initiated is a

Read or Write access to the memory array. The data bus activ ity for the current cycle takes

place two clock cycles later.

CEN

Clock Enable

I

LOW

Synchronous Clock Enable Input. When

CEN is sampled high, all other synchronous inputs,

including clock are ignored and outputs remain unchang ed. The effect of CEN sampled high

on the device outputs is as if the low to high clock transition did not occur. For normal

operation, CEN must be sampled low at rising edge of clock.

Individual Byte

Write Enables

I

LOW

Synchronous by te write enables. Each 9-bit byte has its own active low byte write enable. On

load write cycles (When R/W and ADV/LD are samp led low) the appropriate byte write signal

(

write. Byte Write signals are ignored when R/

W is sampled high. The appropriate byte(s) of

data are written into the device two cycles later.

write to the entire 36-bit word.

Chip Enables

I

LOW

Synchro nous active low chip enable.

IDT71V3548. (

bus will tri-state two clock cycles after deselect is initiated.

Chip Enable

I

HIGH

has inverted polarity but otherwise identical to

CLK

Clock

I

N/A

This is the clock input to the IDT71V3548. Except for

OE, all timing references for the device

are made with respect to the rising edge of CLK.

Data Input/Output

I/O

N/A

Synchronous data input/output (I/O) pins. Both the data input path and data output path are

registered and triggered by the rising edge of CLK.

LBO

Linear Burst Order

I

LOW

Burs t order selection input. When

LBO is high the Interleaved burst sequence is selected.

When

LBO is low the Linear burst sequence is selected. LBO is a static input and it must not

change during device operation.

OE

Output Enable

I

LOW

Asynchronous output enable.

OE must be low to read data from the 71V3548. When OE is

high the I/O pins are in a high-impedance state.

OE does not need to be actively controlled

for read and write cycles. In normal operation,

OE can be tied low.

TMS

Test Mode Select

I

N/A

Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an

internal pullup.

TDI

Test Data Input

I

N/A

Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This

pin has an internal pullup.

TCK

Test Clock

I

N/A

Clo ck input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising

edge of TCK, while test outputs are driven from the falling edge of TCK. This pin has an

internal pullup.

TDO

Test Data Output

O

N/A

Serial output of registers placed between TDI and TDO. This outp ut is active depending on the

state of the TAP controller.

TRST

JTAG Reset

(Optional)

ILOW

Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required.

JTAG reset occurs automatically at power up and also resets using TMS and TCK per IEEE

1149.1. If not used

TRST can be left floating. This pin has an internal pullup.

ZZ

Sleep Mode

I

HIGH

Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the

IDT71V3548 to its lowest power consumption le vel. Data retention is guaranteed in Sleep

Mode. This pin has an internal pulldown

Power Supply

N/A

N/A

3.3V core power supply.

Power Supply

N/A

N/A

3.3V I/O Supply.

Ground

N/A

N/A

Ground.

5296 tbl 02