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5

PR

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IM

IN

AR

Y

OPERATING

CONSIDERATIONS

SA56

GENERAL

Please read Application Note 1 "General Operating Consid-

erations" which covers stability, power supplies, heat sinking,

mounting, and specification interpretation. Visit www.apexmi-

crotech.com for design tools that help automate tasks such as

calculations for stability, internal power dissipation, current limit,

heat sink selection, Apex's complete Application Notes library,

Technical Seminar Workbook and Evaluation Kits.

GROUND PINS

There are 4 GND pins. Pins 9 & 10 are for input signal GND

and pins 1 and 23 are for power gnd.

POWER SUPPLY BYPASSING

Bypass capacitors to power supply terminals Vs and V

DD

must be connected physically close to the pins to prevent

erratic, low efficiency operation and excessive ringing at the

outputs. Electrolytic capacitors, at least 10µF per output amp,

are required for suppressing Vs to PGND noise. High qual-

ity ceramic capacitors (X7R) 1µF or greater should also be

used. Only capacitors rated for switching applications should

be considered.

The bypass capacitors must be located as close to the power

supply pins as possible (due to the very fast switching times

of the outputs, the inductance of 1 inch of circuit trace could

cause noticeable degradation in performance). The bypassing

requirements of V

0.1µF to 0.47µF capacitor connected directly between the V

DD

and GND (SIG) pins will suffice.

PIN DESCRIPTIONS

Pin #

Name

Description

1,23

PGND

Power ground, high current ground

return path of the motor.

2,3

Bout

Half bridge output B

4,5,19,20 VS

High voltage supply

6

SCin

Short circuit detect, CMOS. This pin

can be used as a flag for a short cir-

cuit condition. Under normal operation

this pin will be logic low. When a short

circuit is detected, or output current

exceeds approximately 10A, this pin

will change to logic high and the output

will be latched off. Grounding this pin

disables short circuit protection. This

pin should be left open if short circuit

protection is desired but the flag is not

used. Short circuit protection functions

independently of programmable current

limit (ISEN). It is nessesary to bypass

the SCin pin with a 14-47pF ceramic

capacitor. This capacitor will add a de-

lay to the short circuit response but the

device will still be able to protect itself

against short circuit and over current.

7

TLIM

Temperature limit, CMOS. This pin can

beusedasaflagforanovertemperature

condition. Under normal operation this

pin will be logic low. When junction tem-

perature exceeds approximately 160°C

this pin will change to logic high and

the output will be latched off. Ground-

ing this pin disables over temperature

protection. This pin should be left open

if over temperature protection is desired

but the flag is not used.

8

ISEN/ /ILIM Current Sense output and program-

mable current limit. A current propor-

tional to output current is sourced by

this pin. Typically this pin is connected

to a resistor for programmable current

limit or transconductance operation.

9,10

GND(Sig) Ground connection for all internal digital

and low current analog circuitry.

11

FAULT

Protection circuit flag output, CMOS.

The fault pin will be logic high when the

output MOSFETs have been automati-

callylatchedoffbecauseofashortcircuit

or over temperature condition. This pin

should be left open if not used.

12

CPWM

Anexternaltimingcapacitorisconnected

to this pin to set the frequency of the

internal oscillator and ramp generator

for analog control mode. The capaci-

F

This pin is grounded for digital control

mode.

13,14

VDD

5V supply for input logic and low voltage

analog circuitry.

15

VREF

Reference voltage. Can be used at

low current for biasing analog loop

circuits.

16

DIR

Direction logic input, CMOS/TTL. De-

termines the active output MOSFETs

in two quadrant digital control mode.

This pin should be grounded for analog

control mode.

17

PWM

CMOS/TTL input for digital PWM con-

trol, or 1-4V analog input for duty cycle

control in analog control mode.

18

DISABLE Disable logic input, CMOS/TTL. Logic

low on this pin allows the SA56 to func-

tion normally. When pulled to logic high,

all four output MOSFETs are disabled.

Pulling this pin high, then low will reset

a latched fault condition caused by a

short circuit or over temperature fault.

21,22

Aout

Half bridge output A