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TSC8051C2XXXA16CBD Datasheet(PDF) 10 Page - TEMIC Semiconductors |
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TSC8051C2XXXA16CBD Datasheet(HTML) 10 Page - TEMIC Semiconductors |
10 / 28 page TSC8051C2 Rev. A (10 Jan. 97) 10 Preview MATRA MHS Certain locations in program memory are reserved for specific purposes. Locations 0000h to 0002h are reserved for the initialisation program. Following reset, the CPU always begins execution at location 0000h. Locations 0003h to 002Ah are reserved for the five interrupt request service routines. The internal data memory space is divided into a 256–bytes internal RAM address space and a 128 bytes special function register address space. The internal data RAM address space is 0 to FFh. Four 8–bit register banks occupy locations 0 to 1Fh. 128 bit locations of the internal data RAM are accessible through direct addressing. These bits reside in 16 bytes of internal RAM at location 20h to 2Fh. The stack can be located anywhere in the internal data RAM address space by loading the 8–bit stack pointer (SP SFR). The SFR address space is 100h to 1FFh. All registers except the program counter and the four 8–bit register banks reside in this address space. Memory mapping of the SFRs allows them to be accessed as easily as internal RAM, and as such, they can be operated on by most instructions.The mapping in the SFR address space of the 40 SFRs is shown in Table 2. The SFR names in italic are TSC8051C2 new SFRs and are described in Peripherals Functional Description section. The SFR names in bold are bit addressable. Table 2. Mapping of Special Function Register 0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F F8 PWM8 PWM9 PWM10 PWM11 F0 B PWM4 PWM5 PWM6 PWM7 E8 PWM0 PWM1 PWM2 PWM3 E0 ACC EICON SOCR HWDR MXCR0 D8 PWMCON D0 PSW MXCR1 C8 C0 B8 IP B0 P3 A8 IE MSCON A0 P2 98 SCON SBUF 90 P1 88 TCON TMOD TL0 TL1 TH0 TH1 80 P0 SP DPL DPH PCON 6.8. Interrupts The TSC8051C2 has five interrupt sources, each of which can be assigned one of two priority levels. These five interrupt sources are common to the 80C51 and are the external interrupts (INT0 and INT1), the timer 0 and timer 1 interrupts (IT0 and IT1), and the serial I/O interrupt (RI or TI). |
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