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AS5043TR Datasheet(PDF) 9 Page - ams AG |
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AS5043TR Datasheet(HTML) 9 Page - ams AG |
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9 / 26 page  AS5043 Programmable 360° Magnetic Angle Encoder Revision 1.4, 04-Apr-06 www.austriamicrosystems.com Page 9 of 26 12 Programming the AS5043 After power-on, programming the AS5043 is enabled with the rising edge of CSn and Prog = logic high. 16 bit configuration data must be serially shifted into the OTP register via the Prog-pin. The first “CCW” bit is followed by the zero position data (MSB first) and the Analog Output Mode setting as shown in Table 5. Data must be valid at the rising edge of CLK (see Figure 10). Following this sequence, the voltage at pin Prog must be raised to the programming voltage VPROG (see Figure 11). 16 CLK pulses (tPROG) must be applied to program the fuses. To exit the programming mode, the chip must be reset by a power-on-reset. The programmed data is available after the next power-up. Note: During the programming process, the transitions in the programming current may cause high voltage spikes generated by the inductance of the connection cable. To avoid these spikes and possible damage to the IC, the connection wires, especially the signals PROG and VSS must be kept as short as possible. The maximum wire length between the VPROG switching transistor and pin PROG (Figure 12) should not exceed 50mm (2 inches). To suppress eventual voltage spikes, a 10nF ceramic capacitor should be connected close to pins PROG and VSS. This capacitor is only required for programming, it is not required for normal operation. The clock timing tclk must be selected at a proper rate to ensure that the signal PROG is stable at the rising edge of CLK (see Figure 10). Additionally, the programming supply voltage should be buffered with a 10µF capacitor mounted close to the switching transistor. This capacitor aids in providing peak currents during programming. The specified programming voltage at pin PROG is 7.3 – 7.5V (see section 19.7). To compensate for the voltage drop across the VPROG switching transistor, the applied programming voltage may be set slightly higher (7.5 - 8.0V, see Figure 12). OTP Register Contents: CCW Counter Clockwise Bit ccw=0 – angular value increases with clockwise rotation ccw=1 – angular value increases with counterclockwise rotation Z [9:0]: Programmable Zero / Index Position FB_intEN: OPAMP gain setting: 0=external, 1=internal RefExtEN: DAC reference: 0=internal, 1=external ClampMd EN: Analog output span: 0=0-100%, 1=10-90%*VDD Output Range (OR0, OR1): Analog Output Range Selection [1:0] 00 = 360° 01 = 180° 10 = 90° 11 = 45° Figure 10: Programming Access – OTP Write Cycle (section of Figure 11) Figure 11: Complete OTP programming sequence |
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