11

Figure 3. Recommended Gigabit/sec Ethernet HFBR/HFCT-53D5 Fiber-Optic Transceiver and HDMP-1636A/1646A

SERDES Integrated Circuit Transceiver Interface and Power Supply Filter Circuits.

9

8

7

6

5

4

3

1

PECL

INPUT

OUTPUT

DRIVER

CLOCK

SYNTHESIS

CIRCUIT

PARALLEL

TO SERIAL

CIRCUIT

LASER

DRIVER

CIRCUIT

INPUT

BUFFER

CLOCK

RECOVERY

CIRCUIT

SERIAL TO

PARALLEL

CIRCUIT

PRE-

AMPLIFIER

POST-

AMPLIFIER

SIGNAL

DETECT

CIRCUIT

R10

270

TO SIGNAL DETECT (SD)

INPUT AT UPPER-LEVEL-IC

R11

270

50

Ω

R9

270

R14

100

C12

0.01 µF

C11

0.01 µF

2

C4

10

µF

C3

0.1

µF

5 Vdc

C2

0.1 µF

C1

0.1

µF

C8*

10 µF*

L2

1 µH

L1

1 µH

C10

0.01 µF

C9

0.01 µF

C5

0.1 µF

R1

191

R4

191

R3

68

R2

68

5 Vdc

R13

150

R12

150

50

Ω

50

Ω

50

Ω

+

+

+

3.3 Vdc

GND

TD+

TD-

RD-

RD+

TD+

TD-

RD-

RD+

SD

VCCR

VCCT

VEET

VEER

HFBR/HFCT-53D5

FIBER-OPTIC

TRANSCEIVER

HDMP-1636A/-1646A

SERIAL/DE-SERIALIZER

(SERDES - 10 BIT

TRANSCEIVER)

NOTES:

*C8 IS AN OPTIONAL BYPASS CAPACITOR FOR ADDITIONAL LOW-FREQUENCY NOISE FILTERING.

USE SURFACE-MOUNT COMPONENTS FOR OPTIMUM HIGH-FREQUENCY PERFORMANCE.

USE 50

Ω MICROSTRIP OR STRIPLINE FOR SIGNAL PATHS.

LOCATE 50

Ω TERMINATIONS AT THE INPUTS OF RECEIVING UNITS.

VCC2 VEE2

SEE HDMP-1636A/-1646A DATA SHEET FOR

DETAILS ABOUT THIS TRANSCEIVER IC.