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MCP4922T-EP Datasheet(PDF) 20 Page - Microchip Technology |
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MCP4922T-EP Datasheet(HTML) 20 Page - Microchip Technology |
20 / 40 page MCP4921/4922 DS21897A-page 20 2004 Microchip Technology Inc. 6.0 TYPICAL APPLICATIONS The MCP492X devices are general purpose DACs intended to be used in applications where a precision, low-power DAC with moderate bandwidth is required. Applications generally suited for the MCP492X devices include: • Set Point or Offset Trimming • Sensor Calibration • Digitally-Controlled Multiplier/Divider • Portable Instrumentation (Battery Powered) • Motor Feedback Loop Control 6.1 Digital Interface The MCP492X utilizes a 3-wire syncronous serial protocol to transfer the DACs’ setup and output values from the digital source. The serial protocol can be inter- faced to SPI™ or Microwire peripherals common on many microcontrollers, including Microchip’s PICmicro® MCUs & dsPICTM DSC family of microcon- trollers. In addition to the three serial connections (CS, SCK and SDI), the LDAC signal syncronizes when the serial settings are latched into the DAC’s output from the serial input latch. Figure 6-1 illustrates the required connections. Note that LDAC is active-low. If desired, this input can be tied low to reduce the required con- nections from 4 to 3. Write commands will be latched directly into the output latch when a valid 16 clock transmission has been received and CS has been raised. 6.2 Power Supply Considerations The typical application will require a by-pass capacitor in order to filter high-frequency noise. The noise can be induced onto the power supply's traces or as a result of changes on the DAC's output. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 6-1 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 µF. This capacitor should be placed as close to the device power pin (VDD) as possible (within 4mm). The power source supplying these devices should be as clean as possible. If the application circuit has sep- arate digital and analog power supplies, AVDD and AVSS should reside on the analog plane. FIGURE 6-1: Typical Connection Diagram. 6.3 Layout Considerations Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP492X’s performance. Careful board layout will minimize these effects and increase the signal-to-noise ratio (SNR). Bench testing has shown that a multi-layer board utilizing a low-induc- tance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. Breadboards and wire-wrapped boards are not recommended if low noise is desired. Note: At the time of this data sheet’s release, circuit examples had not completed testing. Your results may vary. VDD VDD VDD AVSS AVSS AVSS VREFA VOUTA VREFB VOUTB 0.1 µF 0.1 µF 0.1 µF VREFA VOUTA VREFB VOUTB SDI SDI CS1 SDO SCK LDAC CS0 |
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