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GS9002 Datasheet(PDF) 4 Page - Gennum Corporation |
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GS9002 Datasheet(HTML) 4 Page - Gennum Corporation |
4 / 11 page 4 520 - 27 - 08 NOT RECOMMENDED FOR NEW DESIGNS The GS9002 Encoder is a bipolar integrated circuit used to convert parallel data into a serial format according to the SMPTE 259M standard. The device encodes both eight and ten bit TTL-compatible parallel signals producing serial data rates up to 400 Mb/s. It operates from a single five volt supply and is packaged in a 44 pin PLCC. Functional blocks within the device include the input latches, sync detector, parallel to serial converter, scrambler, NRZ to NRZ I converter, ECL output buffers for data and clock, PLL for 10x parallel clock multiplication and lock detect. The parallel data (PD0-PD9) and parallel clock (PCK-IN) are applied via pins 7 through 17 respectively. Sync Detector The Sync Detector looks for the reserved words 000-003 and 3FC-3FF, in ten bit Hex, or 00 and FF in eight bit Hex, used in the TRS-ID sync word. When the occurrence of either all zeros or ones at inputs PD2-PD9 is detected, the lower two bits PD0 and PD1 are forced to zeros or ones, respectively. This makes the system compatible with eight or ten bit data. For non - SMPTE standard parallel data, a logic input, Sync Disable (6) is available to disable this feature. Scrambler The Scrambler is a linear feedback shift register used to pseudo-randomize the incoming serial data according to the fixed polynomial (X9+X4+1). This minimizes the DC component in the output serial data stream. The NRZ to NRZI converter uses another polynomial (X+1) to convert a long sequence of ones to a series of transitions, minimizing polarity effects. GS9002 Serial Digital Encoder - Detailed Device Description Phase Locked Loop The PLL performs parallel clock multiplication and provides the timing signal for the serializer. It is composed of a phase/frequency detector, charge pump, VCO and a divide-by-ten counter. The phase/frequency detector allows a wider capture range and faster lock time than that which can be achieved with a phase discriminator alone. The discrimination of frequency also eliminates harmonic locking. With this type of discriminator, the PLL can be over-damped for good stability without sacrificing lock time. The charge pump delivers a 'charge packet' to the loop filter which is proportional to the system phase error. Internal voltage clamps are used to constrain the loop filter voltage between approximately 1.8 and 3.4 volts. The VCO, constructed from a current-controlled multivibrator, features operation in excess of 400 Mb/s and a wide pull range ( ≈±40% of centre frequency). VCO Centre Frequency Selection The wide VCO pull range allows the PLL to compensate for variations in device processing, temperature variations and changes in power supply voltage, without external adjustment. A single external resistor is used to set the VCO current for each of four centre frequencies as selected by a two bit code through a 2:4 decoder. The current setting resistors are connected to the RVCO0 through RVCO3 inputs (34, 33, 32 and 31). The decoder inputs DRS0 and DRS1 (36, 35) are TTL compatible inputs and select the four resistors according to the following truth table. DRS1 DRS0 Resistor Selected 0 0 RVCO0 (34) 0 1 RVCO1 (33) 1 0 RVCO2 (32) 1 1 RVCO3 (31) A 2:1 multiplexer (MUX) selects either the direct data from the P/S Converter (Serializer) or the NRZI data from the Scrambler. This MUX is controlled by the Scrambler/Serializer Select (SSS) input pin 26. When this input is LOW the MUX selects the Scrambler output. (This is the mode used for SMPTE 259M data). When this input is HIGH the MUX directly routes the serialized data to the output buffer with no scrambling or NRZ to NRZ I conversion. The lock detect circuit disables the serial data output when the loop is not locked by turning off the 2:1 MUX. The Lock Detect output is available from pin 20 and is HIGH when the loop is locked. The true and complement serial data, SDO and SDO are available from pins 38 and 39 while the true and complement serial clock, SCK and SCK are available from pins 43 and 42 respectively. If the serial clock is not used pins 43 and 42 can be connected to VCC. The regenerated parallel clock (PCK OUT) is available at pin 19. This output is a single ended pseudo-ECL output requiring a pull down resistor. If regenerated parallel clock is not used pin 19 can be connected to VCC. |
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