GENNUM CORPORATION

18784 - 3

5 of 9

INPUT/OUTPUT CIRCUITS

Fig. 2 Pin 11 SSC

Fig. 3 Pin 14 SCE

Fig. 4 Pins 5 - 8 SDI - SCI

15

SWC

Input

Sync Warning Control. Analog input used to set the HSYNC Error Rate (HER). This is

accomplished by an external RC time constant connected to this pin.

16

PCLK

Output

Parallel Clock Output. CMOS (TTL compatible) clock output where the rising edge of the

clock is located at the centre of the parallel data window within a given tolerance. See Fig. 7.

17

PD0

Output

Parallel Data Output - Bit 0 (LSB). CMOS (TTL compatible) descrambled parallel data output

from the serial to parallel convertor representing the least significant bit (LSB).

18

Power Supply. Most positive power supply connection.

19-25

PD1 - PD7

Outputs

Parallel Data Outputs - Bit 1 to Bit 7. CMOS (TTL compatible) descrambled parallel data

outputs from the serial to parallel convertor representing data bit 1 through data bit 7.

26

Power Supply. Most negative power supply connection.

27

PD8

Output

Parallel Data Output. CMOS (TTL compatible) descrambled parallel data output from the

serial to parallel convertor representing data bit 8.

28

PD9

Output

Parallel Data Output - Bit 9 (MSB). CMOS (TTL compatible) descrambled data output from

the serial to parallel convertor representing the most significant bit (MSB).

PIN DESCRIPTIONS

PIN NO.

SYMBOL

TYPE

DESCRIPTION

EXTERNAL

COMPONENTS

SSC

SCE

SDI

SCI

BIAS

SDI

SCI