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TAS2770RJQT Datasheet(PDF) 57 Page - Texas Instruments |
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TAS2770RJQT Datasheet(HTML) 57 Page - Texas Instruments |
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57 / 100 page  8.5.2.15 TDM_CFG4 (book=0x00 page=0x00 address=0x0E) [reset=13h] Sets TDM TX bus keeper, fill, offset and transmit edge. Figure 8-32. TDM_CFG4 Register Address: 0x0E 7 6 5 4 3 2 1 0 TX_LSB_CFG TX_KEEPER_C FG TX_KEEPER TX_FILL TX_OFFSET[2:0] TX_EDGE RW-0h RW-0h RW-0h RW-1h RW-1h RW-1h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-96. TDM Configuration 4 Field Descriptions Bit Field Type Reset Description 7 TX_LSB_CFG RW 0h TDM TX SDOUT LSB data option 0b = TX SDOUT LSB is driven for full-cycle (provided TX_KEEPER is '0') 1b = TX SDOUT LSB is driven for half-cycle 6 TX_KEEPER_CFG RW 0h TDM TX SDOUT bus keeper configuration. 0b = Bus keeper is enabled only for 1 LSB bit cycle & SDOUT LSB driven for half cycle (provided TX_KEEPER is '1') 1b = Bus keeper is always enabled & SDOUT LSB driven for half cycle (provided TX_KEEPER is '1') 5 TX_KEEPER RW 0h TDM TX SDOUT bus keeper enable. 0b = Disable bus keeper 1b = Enable bus keeper 4 TX_FILL RW 1h TDM TX SDOUT unused bitfield fill. 0b = Transmit 0 1b = Transmit Hi-Z 3-1 TX_OFFSET[2:0] RW 1h TDM TX start of frame to time slot 0 offset. 0 TX_EDGE RW 1h TDM TX launch clock polarity. 0b = Rising edge of SBCLK 1b = Falling edge of SBCLK 8.5.2.16 TDM_CFG5 (book=0x00 page=0x00 address=0x0F) [reset=2h] Sets TDM TX V-Sense time slot and enable. Figure 8-33. TDM_CFG5 Register Address: 0x0F 7 6 5 4 3 2 1 0 Reserved VSNS_TX VSNS_SLOT[5:0] RW-0h RW-0h RW-2h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 8-97. TDM Configuration 5 Field Descriptions Bit Field Type Reset Description 7 Reserved RW 0h Reserved 6 VSNS_TX RW 0h TDM TX voltage sense transmit enable. 0b = Disabled 1b = Enabled 5-0 VSNS_SLOT[5:0] RW 2h TDM TX voltage sense time slot. It is recommended to maintain the following order: ISNS_SLOT<VSNS_SLOT<PDM_SLOT<VBAT_SLOT<TEMP_ SLOT<GAIN_SLOT 8.5.2.17 TDM_CFG6 (book=0x00 page=0x00 address=0x10) [reset=0h] Sets TDM TX I-Sense time slot and enable. www.ti.com TAS2770 SLASEM6D – OCTOBER 2017 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: TAS2770 |
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