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FPGA-DS-02013-1.7 Datasheet(PDF) 39 Page - Lattice Semiconductor |
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FPGA-DS-02013-1.7 Datasheet(HTML) 39 Page - Lattice Semiconductor |
39 / 57 page CrossLink Automotive Family Data Sheet © 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02013-1.7 39 Generic DDRX71 Outputs with Clock and Data Aligned at Pin (GDDRX71_TX.ECLK) tTPBi_DOV Data Output Valid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) — — 0.143 ns+i*UI tTPBi_DOI Data Output Invalid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) — −0.143 — ns+i*UI tTPBi_skew_UI Tx skew in UI — — 0.15 UI fMAX_TX71 DDR71 ECLK Frequency 2 — — 525 MHz Generic DDRX141 Outputs with Clock and Data Aligned at Pin (GDDRX141_TX.ECLK) tTPBi_DOV Data Output Valid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) All Devices — 0.125 ns+i*UI tTPBi_DOI Data Output Invalid Bit "i" switching from CLK Rising Edge ("i" = 0 to 6, 0 aligns with CLK) All Devices −0.125 — ns+i*UI tTPBi_skew_UI TX skew in UI All Devices — 0.15 UI fMAX_TX141 DDR141 ECLK Frequency 2 — — 600 MHz Notes: 1. Generic DDRX8, DDRX71 and DDRX141 timing numbers based on LVDS I/O. 2. Maximum clock frequencies are tested under best case conditions. System performance may vary upon the user environment. 3. These numbers are generated using best case PLL location. 4. All numbers are generated with the Lattice Diamond design software. 5. Maximum data rate for GDDRX2 mode is 600 Mbps. tSU/tDVBDQ Rx CLK (in) Rx DATA (in) tHD/tDVADQ tSU/tDVBDQ tHD/tDVADQ Figure 4.1. Receiver RX.CLK.Centered Waveforms |
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