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FPGA-DS-02013-1.7 Datasheet(PDF) 10 Page - Lattice Semiconductor

Part # FPGA-DS-02013-1.7
Description  CrossLink Automotive Family
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

FPGA-DS-02013-1.7 Datasheet(HTML) 10 Page - Lattice Semiconductor

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CrossLink Automotive Family
Data Sheet
© 2016-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
FPGA-DS-02013-1.7
3.1. MIPI D-PHY Blocks
The top side of the device (Figure 3.2) includes two hard MIPI D-PHY quads. The D-PHY can be configured to support
both camera interface (CSI-2) and display interface (DSI) applications. Below is a summary of the features supported by
the hard D-PHY quads.
Transmit and Receive compliant to MIPI Alliance Specification D-PHY Revision 1.1
High-Speed (HS) and Low-Power (LP) mode support (including built-in contention detect)
Supports continuous clock mode or low power clock mode
Up to 6 Gb/s per quad (1500 Mb/s data rate per lane)
Dedicated PLL for Transmit Frequency Synthesis
Dedicated Serializer and De-Serializer blocks for fabric interfacing. Lattice Semiconductor provides a set of pre-
engineered IP modules which include the full implementation and control of the hard D-PHY blocks to enable designers
to focus on unique aspects of their design.
Lattice Semiconductor provides a set of pre-engineered IP modules, which includes the full implementation and control
of the hard D-PHY blocks to enable designers to focus on unique aspects of their design.
Figure 3.3 to Figure 3.6 show the signals connected to the fabric and the automatic settings when the hardened D-PHY
is configured for the DSI/CSI-2 transmit and receive modes. Refer to CrossLink High-Speed I/O Interface (FPGA-TN-
02012) for more information on the Hard D-PHY quads.
MIPI D-PHY 0
MIPI D-PHY 1
Bank 0
Bank 1
Bank 2
TOP
BOTTOM
Figure 3.2. CrossLink Automotive sysI/O Banking


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