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FPGA-DS-02074-3.1 Datasheet(PDF) 3 Page - Lattice Semiconductor

Part # FPGA-DS-02074-3.1
Description  Lattice ECP3 Family Data Sheet
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Manufacturer  LATTICE [Lattice Semiconductor]
Direct Link  http://www.latticesemi.com
Logo LATTICE - Lattice Semiconductor

FPGA-DS-02074-3.1 Datasheet(HTML) 3 Page - Lattice Semiconductor

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LatticeECP3 Family Data Sheet
Data Sheet
© 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-DS-02074-3.1
3
Contents
1.
Introduction..................................................................................................................................................................9
1.1.
Features ..............................................................................................................................................................9
1.2.
Introduction ......................................................................................................................................................10
2.
Architecture................................................................................................................................................................11
2.1.
Architecture Overview ......................................................................................................................................11
2.2.
PFU Blocks .........................................................................................................................................................12
2.2.1.
Slice ..............................................................................................................................................................13
2.2.2.
Modes of Operation .....................................................................................................................................15
2.3.
Routing ..............................................................................................................................................................16
2.4.
sysCLOCK PLLs and DLLs ....................................................................................................................................16
2.4.1.
General Purpose PLL.....................................................................................................................................16
2.4.2.
Delay Locked Loops (DLL) .............................................................................................................................17
2.4.3.
PLL/DLL Cascading ........................................................................................................................................19
2.4.4.
PLL/DLL PIO Input Pin Connections ..............................................................................................................19
2.5.
Clock Dividers ....................................................................................................................................................20
2.6.
Clock Distribution Network ...............................................................................................................................20
2.6.1.
Primary Clock Sources ..................................................................................................................................20
2.6.2.
Primary Clock Routing ..................................................................................................................................22
2.6.3.
Dynamic Clock Control (DCC) .......................................................................................................................23
2.6.4.
Dynamic Clock Select (DCS) ..........................................................................................................................23
2.6.5.
Secondary Clock/Control Sources ................................................................................................................23
2.6.6.
Secondary Clock/Control Routing ................................................................................................................24
2.6.7.
Slice Clock Selection .....................................................................................................................................26
2.6.8.
Edge Clock Sources.......................................................................................................................................26
2.6.9.
Edge Clock Routing .......................................................................................................................................27
2.7.
sysMEM Memory ..............................................................................................................................................29
2.7.1.
sysMEM Memory Block................................................................................................................................29
2.7.2.
Bus Size Matching.........................................................................................................................................29
2.7.3.
RAM Initialization and ROM Operation........................................................................................................29
2.7.4.
Memory Cascading .......................................................................................................................................29
2.7.5.
Single, Dual and Pseudo-Dual Port Modes...................................................................................................30
2.7.6.
Memory Core Reset......................................................................................................................................30
2.8.
sysDSP™ Slice ....................................................................................................................................................30
2.8.1.
sysDSP Slice Approach Compared to General DSP .......................................................................................30
2.9.
LatticeECP3 sysDSP Slice Architecture Features ...............................................................................................31
2.9.1.
MULT DSP Element.......................................................................................................................................33
2.9.2.
MAC DSP Element ........................................................................................................................................34
2.9.3.
MMAC DSP Element .....................................................................................................................................35
2.9.4.
MULTADDSUB DSP Element .........................................................................................................................36
2.9.5.
MULTADDSUBSUM DSP Element .................................................................................................................37
2.10.
Advanced sysDSP Slice Features .......................................................................................................................38
2.10.1. Cascading......................................................................................................................................................38
2.10.2. Addition........................................................................................................................................................38
2.10.3. Rounding ......................................................................................................................................................38
2.10.4. ALU Flags ......................................................................................................................................................38
2.10.5. Clock, Clock Enable and Reset Resources.....................................................................................................38
2.10.6. Resources Available in the LatticeECP3 Family ............................................................................................38
3.
Programmable I/O Cells (PIC) .....................................................................................................................................40
3.1.
PIO.....................................................................................................................................................................42
3.1.1.
Input Register Block .....................................................................................................................................42
3.1.2.
Output Register Block...................................................................................................................................43
3.1.3.
Tristate Register Block..................................................................................................................................44


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