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FPGA-DS-02074-3.1 Datasheet(PDF) 12 Page - Lattice Semiconductor |
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FPGA-DS-02074-3.1 Datasheet(HTML) 12 Page - Lattice Semiconductor |
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12 / 147 page  LatticeECP3 Family Data Sheet Data Sheet © 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 FPGA-DS-02074-3.1 Configuration Logic: Dual-boot, Encryption and Transparent Updates Pre-engineered Source Synchronous Support: DDR3 - 800 Mbps Generic - Up to 1 Gbps Figure 2.1. Simplified Block Diagram, LatticeECP3-35 Device (Top Level) 2.2. PFU Blocks The core of the LatticeECP3 device consists of PFU blocks, which are provided in two forms, the PFU and PFF. The PFUs can be programmed to perform Logic, Arithmetic, Distributed RAM and Distributed ROM functions. PFF blocks can be programmed to perform Logic, Arithmetic and ROM functions. Except where necessary, the remainder of this data sheet will use the term PFU to refer to both PFU and PFF blocks. Each PFU block consists of four interconnected slices numbered 0-3 as shown in Figure 2.2. Each slice contains two LUTs. All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated with each PFU block. |
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