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FPGA-DS-02074-3.1 Datasheet(PDF) 21 Page - Lattice Semiconductor |
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FPGA-DS-02074-3.1 Datasheet(HTML) 21 Page - Lattice Semiconductor |
21 / 147 page LatticeECP3 Family Data Sheet Data Sheet © 2015-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-DS-02074-3.1 21 Note: Clock inputs can be configured in d ifferential or s ingle-ended mode. Figure 2.9. Primary Clock Sources for LatticeECP3-17 Note: Clock inputs can be configured in differential or single-ended mode. Figure 2.10. Primary Clock Sources for LatticeECP3-35 |
Similar Part No. - FPGA-DS-02074-3.1 |
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Similar Description - FPGA-DS-02074-3.1 |
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