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AD5290YRMZ50-RL7 Datasheet(PDF) 4 Page - Analog Devices |
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AD5290YRMZ50-RL7 Datasheet(HTML) 4 Page - Analog Devices |
4 / 11 page Preliminary Technical Data AD5290 Rev. Pr C | Page 4 of 11 TIMING CHARACTERISTICS— 10 kΩ, 50 kΩ, 100 kΩ VERSIONS (VDD/VSS = ±15V±10% or ±5V±10%, VA = +VDD, VB = 0V, -40°C < TA < +105°C unless otherwise noted.) Table 2. Parameter Symbol Conditions Min Typ1 Max Unit SPI INTERFACE TIMING CHARACTERISTICS6, 8,9 (Specifications Apply to All Parts) Clock Frequency fCLK 4 MHz Input Clock Pulsewidth tCH, tCL Clock level high or low 120 ns Data Setup Time tDS 30 ns Data Hold Time tDH 20 ns CLK to SDO Propagation Delay tPD RPU = 1KΩ, CL < 20pF 10 100 ns CS Setup Time tCSS 120 ns CS High Pulsewidth tCSW 150 ns CLK Fall to CS Fall Hold Time tCSH0 TBD ns CLK Fall to CS Rise Hold Time tCSH1 120 ns CS Rise to Clock Rise Setup tCS1 120 ns NOTES 1. Typical specifications represent average readings at +25°C and VDD = 5 V. 2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3. VAB = VDD, Wiper (VW) = no connect. 4. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA=VDD and VB=0 V. 5. Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6. Guaranteed by design and not subject to production test. 7. PDISS is calculated from (IDD × VDD+ ISS × VSS) CMOS logic level inputs result in minimum power dissipation. 8. All dynamic characteristics use VDD / VSS = ±5 V. 9. See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. |
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