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TAAD08JU2 Datasheet(PDF) 9 Page - Agere Systems |
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TAAD08JU2 Datasheet(HTML) 9 Page - Agere Systems |
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9 / 174 page  List of Tables Table Page Agere Systems Inc. Agere Systems - Proprietary 9 Use pursuant to Company instructions Data Sheet TAAD08JU2 August 18, 2003 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 Table 1. Pin Definitions................................................................................................................................... 12 Table 2. Transmission Line Interface Signals (48 Signals) ............................................................................ 13 Table 3. CHI Interface Signals (20 Signals) ................................................................................................... 14 Table 4. UTOPIA 2 Expansion Interface Signals (52 Signals) ....................................................................... 14 Table 5. System Interface Signals (62 Signals).............................................................................................. 15 Table 6. Switch Fabric Interface Signals (50 Pins)......................................................................................... 17 Table 7. APC External Statistics Interface Signals (18 Signals) .................................................................... 18 Table 8. SAR External Statistics Interface Signals (18 Signals)..................................................................... 18 Table 9. Host Interface Signals (49 Signals) .................................................................................................. 19 Table 10. JTAG Interface Pins (6 Signals) ...................................................................................................... 19 Table 11. Global/Miscellaneous Signal Pins (10 Signals) ................................................................................ 19 Table 12. Power Supply Pins (4 Analog Power Pins, 120 Digital Power Pins) ............................................... 20 Table 13. Signal-to-Ball Mapping ..................................................................................................................... 22 Table 14. Host Registers .................................................................................................................................. 50 Table 15. Frame Alignment Criteria.................................................................................................................. 58 Table 16. Performance Monitor Functional Descriptions.................................................................................. 59 Table 17. Performance Report Message Format ............................................................................................. 61 Table 18. Performance Report Message Field Definition ................................................................................. 62 Table 19. Shared Tx Stack Format for CEPT Frame ....................................................................................... 65 Table 20. Cell Headers of Idle, Unassigned, and Invalid Cells......................................................................... 73 Table 21. TC Functionality................................................................................................................................ 73 Table 22. TAAD08JU2 Exceptions to the IMA PICS Proforma ........................................................................ 85 Table 23. PATM Fields ................................................................................................................................... 114 Table 24. HPF Fields...................................................................................................................................... 115 Table 25. ESI Message Format (AALXDATA[15:0])....................................................................................... 116 Table 26. ESI Violation Codings..................................................................................................................... 117 Table 27. AAL Type vs. Service Type Compatibility....................................................................................... 118 Table 28. Transport of Congestion Indication and Loss Priority..................................................................... 121 Table 29. PortIndex to Enqueue Block Port Mapping..................................................................................... 123 Table 30. MEMI-SM Resources ..................................................................................................................... 124 Table 31. SQASE-SM Resources .................................................................................................................. 130 Table 32. L1Q and IL2Q Scheduling .............................................................................................................. 135 Table 33. Example Stage-Two Divider Settings ............................................................................................. 137 Table 34. Exceptions ...................................................................................................................................... 141 Table 35. Absolute Maximum Ratings............................................................................................................ 154 Table 36. Power Requirements ...................................................................................................................... 154 Table 37. Operating Conditions...................................................................................................................... 154 Table 38. Handling Precautions ..................................................................................................................... 155 Table 39. Version 2.1 Logic Interface Characteristics .................................................................................... 155 Table 40. Version 3.1 Logic Interface Characteristics .................................................................................... 156 Table 41. Versions 2.1 and 3.1 Main System Clock (GCLK) Timing Specifications....................................... 157 Table 42. Version 2.1 UTOPIA Input Clocks (UCLK) Timing Specifications .................................................. 157 Table 43. Version 3.1 UTOPIA Input Clocks (UCLK_A[B]) Timing Specifications ......................................... 157 Table 44. Host Read Timing Characteristics .................................................................................................. 158 Table 45. Host Write Timing Characteristics .................................................................................................. 159 Table 46. Version 2.1 CHI Transmit Timing Characteristics........................................................................... 161 Table 47. Version 3.1 CHI Transmit Timing Characteristics........................................................................... 161 Table 48. CHI Receive Timing Characteristics............................................................................................... 162 Table 49. Version 2.1 Fabric Interface Timing Specifications (Transmit Interface) ........................................ 162 Table 50. Version 3.1 Fabric Interface Timing Specifications (Transmit Interface) ........................................ 163 Table 51. Version 2.1 Fabric Interface Timing Specifications (Receive Interface) ......................................... 163 Table 52. Version 3.1 Fabric Interface Timing Specifications (Receive Interface) ......................................... 163 |
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