Data Sheet, Revision 1

LCK4993/LCK4994

May 5, 2004

Low-Voltage PLL Clock Drivers

Agere Systems Inc.

11

5.9 Factory Test Mode Description

The device will enter factory test mode when the OUTPUT_MODE input is driven to a mid level. In factory test mode, the

device will operate with its internal PLL disconnected. The reference input will replace the PLL output. While operating in

factory test mode, the selected FB input(s) must both be tied low. The output frequency is a function of the input level set on

the FS pin (see Table 5-6). When operating in factory test mode, all outputs must be set to the divide by 1 function. Output

skew select function operates normally, output bank disable is unavailable while operating in factory test mode. The

OUTPUT_MODE input is designed to be a static input. Dynamically toggling this input from low to high may temporarily

cause the device to go into factory test mode (when passing through the mid state).

5.9.1 Factory Test Reset

When operating in factory test mode (OUTPUT_MODE = mid), the device can be reset to a deterministic state by forcing

the DIS4 input to a logic high. With DIS4 in a logic high state, all clock outputs will go to HI-Z. After the selected reference

clock pin has five positive transitions, all the internal finite state machines (FSM) will be set to a deterministic state. The

deterministic state of the state machines will depend on the configuration of the divide select, skew select, and frequency

select inputs. All clock outputs will stay in high-impedance mode, and all FSMs will stay in the deterministic state until DIS4

is deasserted. When DIS4 is deasserted (with OUTPUT_MODE still at mid), the device will re-enter factory test mode.

5.10 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute

stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those

given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can

adversely affect device reliability.

Table 5-6. Factory Test Mode Frequency Divide Select

FS

LCK4993

LCK4994

Output Frequency

Output Frequency

Divide By

Divide By

Low

32

16

Mid

16

8

High

8

4

Table 5-7. Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Unit

Storage Temperature

–40

125

°C

Supply Voltage

–0.5

4.6

V

dc Input Voltage

–0.3

V

Output Current into Outputs (low)

—40

mA

Latch-Up Current

—±200

mA