MITSUBISHI

〈DIGITAL ASSP〉

M66007P/FP

12-BIT INPUT EXPANDER

1

MITSUBISHI

〈DIGITAL ASSP〉

M66007P/FP

12-BIT INPUT EXPANDER

DESCRIPTION

The M66007 is a semiconductor integrated circuit providing

the 12-bit parallel input-serial output shift register function.

This product is completely designed with CMOS to sharply

reduce power consumption compared with bipolar or Bi-

CMOS product.

The M66007, developed as an input only expander IC neces-

sary for microcomputer periphery, is widely applicable as a

data parallel/serial conversion IC.

FEATURES

• Control signals of only two pins including LE/D and CLK

• Low power consumption of 50 µW/package maximum

(Vcc=5V, Ta=25°C at time of standstill)

• Schmitt triggered input (LE/D, CLK, D0 to D11)

• Wide operating supply voltage range (Vcc=2~6V)

• Wide operating temperature range (Ta=–20~75°C)

APPLICATION

Parallel/serial data conversion for microcomputer periphery

FUNCTION

The M66007 uses a silicon gate CMOS process to achieve

low power consumption and high noise margin.

For control signals, this IC adopts only the two pins of latch

input/serial data output LE/D and clock input CLK. Each bit

of shift register of 12-bit parallel input-serial output consists of

flip-flop for shift.

When LE/D is placed in input mode, CLK is set to “H” and LE/

D changes from “H” to “L”, the status of parallel data inputs D0

to D11 at that time is latched with the flip-flop for shift and LE/

D is switched to output mode to output “L”.

PIN CONFIGURATION (TOP VIEW)

BLOCK DIAGRAM

Outline 16P4

16P2N-A

After this, change of CLK from “H” to “L” makes the shift regis-

ter perform shift operation and LE/D outputs the contents of

the shift register from D0 in order.

In addition, the shift operation for up to the 12th bit is carried

out and then LE/D is switched to the input mode at the falling

edge of CLK of the 13th bit.

When power is turned on, the input/output mode of LE/D is

indeterminate. However, detection of 13 or more falling

edges of CLK sets LE/D in the input mode.

LE/D

CLK

D11

D10

D9

D8

D7

D6

D5

D0

D1

D3

LE/D ↔

CLK →

D0 →

D1 →

D2 →

D3 →

D4 →

GND

← D11

← D10

← D9

← D8

← D7

← D6

← D5









































































LATCH INPUT/

SERIAL DATA OUTPUT

116

215

314

413

512

611

710

89

PARALLEL

DATA INPUT

CLOCK INPUT

PARALLEL

DATA INPUT

D2

D4

1

2

8

16

15

14

13

12

11

10

9

7

6

5

4

3

GND

Vcc

CLK

LE/D

Vcc

LCLK

CLK

SQ

SD

LE

LE

LATCH INPUT/

SERIAL DATA OUTPUT

CLOCK INPUT

PARALLEL DATA INPUT

PARALLEL LATCH

SHIFT REGISTER

CONTROL CIRCUIT