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HT47C20-1 Datasheet(PDF) 9 Page - Holtek Semiconductor Inc |
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HT47C20-1 Datasheet(HTML) 9 Page - Holtek Semiconductor Inc |
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9 / 43 page  HT47R20A-1/HT47C20-1 Rev. 1.70 9 June 14, 2005 from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledgment will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow al- lowing the programmer to use the structure more easily. In a similar case, if the stack is full and a ²CALL² is sub- sequently executed, stack overflow occurs and the first entry will be lost (only the most recent four return ad- dresses are stored). Data Memory - RAM The data memory is designed with 85 ´8 bits. The data memory and is divided into two functional groups: spe- cial function registers and general purpose data mem- ory (64 ´8). Most are read/write, but some are read only. The special function registers include the indirect ad- dressing register 0 (00H), the memory pointer register 0 (mp0; 01H), the indirect addressing register 1 (02H), the memory pointer register 1 (MP1;03H), the bank pointer (BP;04H), the accumulator (ACC;05H), the program counter lower-order byte register (PCL;06H), the table pointer (TBLP;07H), the table higher-order byte register (TBLH;08H), the real time clock control register (RTCC;09H), the status register (STATUS;0AH), the in- terrupt control register 0 (INTC0;0BH), the I/O registers (PA;12H, PB;14H), the interrupt control register 1 (INTC1;1EH), the timer/event counter A higher order byte register (TMRAH;20H), the timer/event counter A lower or- der byte register (TMRAL;21H), the timer/event counter control register (TMRC;22H), the timer/event counter B higher order byte register (TMRBH;23H), the timer/event counter B lower order byte register (TMRBL;24H), and the RC oscillator type A/D converter control register (ADCR; 25H). The remaining space before the 40H are reserved for future expanded usage and reading these location will return the result 00H. The general purpose data memory, addressed from 40H to 7FH, is used for data and control information under instruction command. All data memory areas can handle arithmetic, logic, in- crement, decrement and rotate operations. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instruction, respectively. They are also indirectly accessible through memory pointer registers (MP0;01H, MP1;03H). G e n e r a l P u r p o s e D a t a M e m o r y ( 6 4 B y t e s ) 7 F H 2 0 H I N T C 1 T M R A H T M R A L T M R C T M R B H T M R B L A D C R 2 1 H 2 2 H 2 3 H 2 4 H 2 5 H 2 6 H 4 0 H S p e c i a l P u r p o s e D a t a M e m o r y 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H 1 9 H 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H : U n u s e d R e a d a s " 0 0 " I n d i r e c t A d d r e s s i n g R e g i s t e r 0 M P 0 P A P B M P 1 B P A C C P C L T B L P T B L H R T C C S T A T U S I N T C 0 I n d i r e c t A d d r e s s i n g R e g i s t e r 1 RAM Mapping (Bank 0) |
Similar Part No. - HT47C20-1 |
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Similar Description - HT47C20-1 |
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