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HT48E10 Datasheet(PDF) 5 Page - Holtek Semiconductor Inc |
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HT48E10 Datasheet(HTML) 5 Page - Holtek Semiconductor Inc |
5 / 41 page HT48E10 Rev. 1.20 5 March 3, 2006 Functional Description Execution Flow The HT48E10 system clock is derived from either a crystal or an RC oscillator and is internally divided into four non-overlapping clocks. One instruction cycle con- sists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes an instruction cycle while de- coding and execution takes the next instruction cycle. This pipelining scheme ensures that instructions are ef- fectively executed in one cycle. If an instruction changes the contents of the program counter, such as subroutine calls or jumps, in which case, two cycles are required to complete the instruction. Program Counter - PC The program counter (PC) controls the sequence in which the instructions stored in the program ROM are executed and its contents specify a full range of pro- gram memory. After accessing a program memory word to fetch an in- struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading into the PCL register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupt, the PC man- ages the program transfer by loading the address corre- sponding to each instruction. The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a read- able and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within the 256 locations. When a control transfer takes place, an additional dummy cycle is required. Mode Program Counter *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 Initial Reset 0000000000 External Interrupt 0000000100 Timer/Event Counter Overflow 0000001000 Skip Program Counter+2 Loading PCL *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 Jump, Call Branch #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *9~*0: Program counter bits S9~S0: Stack register bits #9~#0: Instruction code bits @7~@0: PCL bits T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 F e t c h I N S T ( P C ) E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 ) E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 ) E x e c u t e I N S T ( P C + 1 ) P C P C + 1 P C + 2 S y s t e m C l o c k O S C 2 ( R C o n l y ) P C Execution Flow |
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