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HT48C50-1 Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
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HT48C50-1 Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
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11 / 41 page  HT48R50A-1/HT48C50-1 Rev. 2.00 11 March 8, 2006 OSC). Also, the frequencies of the internal RC oscillator can be 3.2MHz, 1.6MHz, 800kHz and 400kHz (depends on the options). The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the sys- tem enters the power down mode, the system clock is stopped, but the WDT oscillator still works within a period of 65 ms at 5V. The WDT oscillator can be disabled by op- tions to conserve power. Watchdog Timer - WDT The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator), RTC clock or instruction clock (system clock divided by 4), determines the op- tions. This timer is designed to prevent a software mal- function or sequence from jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by options. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation. The RTC clock is enabled only in the in- ternal RC+RTC mode. Once the internal WDT oscillator (RC oscillator with a period of 65 ms at 5V normally) is selected, it is first di- vided by 256 (8-stage) to get the nominal time-out pe- riod of 17ms at 5V. This time-out period may vary with temperatures, VDD and process variations. By invoking the WDT prescaler, longer time-out periods can be real- ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the WDTS) can give different time-out periods. If WS2, WS1, and WS0 are all equal to 1, the division ratio is up to 1:128, and the maximum time-out period is 2.1s at 5V seconds. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and oper- ates in the same manner except that in the HALT state the WDT may stop counting and lose its protecting pur- pose. In this situation the logic can only be restarted by external logic. The high nibble and bit 3 of the WDTS are reserved for user's defined flags, which can be used to indicate some specified status. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) or 32kHz crystal oscilla- tor (RTC OSC) is strongly recommended, since the HALT will stop the system clock. WS2 WS1 WS0 Division Ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 WDTS (09H) Register The WDT overflow under normal operation will initialize ²chip reset² and set the status bit ²TO². But in the HALT mode, the overflow will initialize a ²warm reset² and only the Program Counter and SP are reset to zero. To clear the contents of WDT (including the WDT prescaler), three methods are adopted; external reset (a low level to RES), software instruction and a ²HALT² instruction. The software instruction include ²CLR WDT² and the other set -²CLR WDT1² and ²CLR WDT2². Of these two types of instruction, only one can be active depend- ing on the option -²CLR WDT times selection option².If the ²CLR WDT² is selected (i.e. CLRWDT times equal one), any execution of the ²CLR WDT² instruction will clear the WDT. In the case that ²CLR WDT1² and ²CLR WDT2 ² are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out. Power Down Operation - HALT The HALT mode is initialized by the ²HALT² instruction and results in the following... · The system oscillator will be turned off but the WDT oscillator remains running (if the WDT oscillator is se- lected). · The contents of the on chip RAM and registers remain unchanged. · WDT and WDT prescaler will be cleared and re- counted again (if the WDT clock is from the WDT os- cillator). S y s t e m C l o c k / 4 8 - b i t C o u n t e r W D T P r e s c a l e r 7 - b i t C o u n t e r 8 - t o - 1 M U X W D T T i m e - o u t W S 0 ~ W S 2 O p t i o n S e l e c t W D T O S C R T C O S C Watchdog Timer |
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