HT48RA0-1/HT48CA0-1

Rev. 1.40

7

December 21, 2005

Oscillator Configuration

There are two oscillator circuits implemented in the

microcontroller.

Both are designed for system clocks; the RC oscillator

and the Crystal oscillator, which are determined by code

options. No matter what oscillator type is selected, the

signal provides the system clock. The HALT mode stops

the system oscillator and ignores the external signal to

conserve power.

If an RC oscillator is used, an external resistor between

OSC1 and VSS in needed and the resistance must

range from 51k

W to 1MW. The system clock, divided by

4, is available on OSC2, which can be used to synchro-

nize external logic. The RC oscillator provides the most

cost effective solution. However, the frequency of the

itself due to process variations. It is, therefore, not suit-

able for timing sensitive operations where accurate os-

cillator frequency is desired.

If the Crystal oscillator is used, a crystal across OSC1

and OSC2 is needed to provide the feedback and phase

shift for the oscillator. No other external components are

needed. Instead of a crystal, the resonator can also be

connected between OSC1 and OSC2 to get a frequency

reference, but two external capacitors in OSC1 and

OSC2 are required.

Watchdog Timer

- WDT

The clock source of the WDT is implemented by instruc-

tion clock (system clock divided by 4). The clock source

is processed by a frequency divider and a prescaller to

yield various time out periods.

WDT time out period =

Clock Source

2

n

Where n= 8~11 selected by code option.

Bit No.

Label

Function

0C

C is set if the operation results in a carry during an addition operation or if a borrow does not

take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro-

tate through carry instruction.

1AC

AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from

the high nibble into the low nibble in subtraction; otherwise AC is cleared.

2

Z

Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.

3OV

OV is set if the operation results in a carry into the highest-order bit but not a carry out of the

highest-order bit, or vice versa; otherwise OV is cleared.

4

PDF

PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF

is set by executing the HALT instruction.

5TO

TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is

set by a WDT time-out.

6~7

¾

Unused bit, read as

²0²

Status (0AH) Register

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

O S C 1

O S C 2

( N M O S o p e n

d r a i n o u t p u t )

System Oscillator

2 n

C l o c k S o u r c e

( S y s t e m C l o c k / 4 )

3 - b i t C o u n t e r

P r e s c a l l e r

( 8 - b i t )

W D T

T i m e - o u t

C o d e O p t i o n

S e l e c t

C o d e

O p t i o n

C l e a r W D T

F r e q u e n c y D i v i d e r

C l o c k S o u r c e

( n = 8 ~ 1 1 )

Watchdog Timer