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ADC14L040 Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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ADC14L040 Datasheet(HTML) 7 Page - National Semiconductor (TI) |
7 / 23 page DC and Logic Electrical Characteristics (Continued) Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V A =VD = +3.3V, VDR = +2.5V, PD = 0V, External V REF = +1.0V, fCLK = 40 MHz, fIN = 20 MHz, tr =tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for T J =TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) Power Down Power Consumption PD Pin = V D, clock on 15 mW PSRR Power Supply Rejection Ratio Rejection of Full-Scale Error with V A =3.0V vs. 3.6V 72 dB AC Electrical Characteristics Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V A =VD = +3.3V, VDR = +2.5V, PD = 0V, External V REF = +1.0V, fCLK = 40 MHz, fIN = 10 MHz, tr =tf = 2 ns, CL = 15 pF/pin, Duty Cycle Stabilizer On. Boldface limits apply for T J =TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 12) Symbol Parameter Conditions Typical (Note 10) Limits (Note 10) Units (Limits) f CLK1 Maximum Clock Frequency 40 MHz (min) f CLK2 Minimum Clock Frequency 5 MHz t CH Clock High Time Duty Cycle Stabilizer On 12.5 5 ns (min) t CL Clock Low Time Duty Cycle Stabilizer On 12.5 5 ns (min) t CH Clock High Time Duty Cycle Stabilizer Off 12.5 10 ns (min) t CL Clock Low Time Duty Cycle Stabilizer Off 12.5 10 ns (min) t CONV Conversion Latency 7 Clock Cycles t OD Data Output Delay after Rising Clock Edge 6 9.6 ns (max) t AD Aperture Delay 2 ns t AJ Aperture Jitter 0.7 ps rms t PD Power Down Mode Exit Cycle 0.1 µF on pins 30, 31, 32; 10 µF between pins 30, 31 280 µs Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified. Note 3: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. Note 4: The absolute maximum junction temperature (TJmax) for this device is 150˚C. The maximum allowable power dissipation is dictated by TJmax, the junction-to-ambient thermal resistance ( θJA), and the ambient temperature, (TA), and can be calculated using the formula PDMAX=(TJmax - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Obviously, such conditions should always be avoided. Note 5: Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through 0Ω. Note 6: Reflow temperature profiles are different for lead-free and non-lead-free packages. Note 7: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per (Note 3). However, errors in the A/D conversion can occur if the input goes above VA or below GND by more than 100 mV. As an example, if VA is +3.3V, the full-scale input voltage must be ≤+3.4V to ensure accurate conversions. 20146511 Note 8: To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin. Note 9: With the test condition for VREF = +1.0V (2VP-P differential input), the 14-bit LSB is 122.1 µV. Note 10: Typical figures are at TJ = 25˚C, and represent most likely parametric norms. Test limits are guaranteed to National’s AOQL (Average Outgoing Quality Level). www.national.com 7 |
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