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M66255FP Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor |
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M66255FP Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor |
1 / 11 page 1 MITSUBISHI 〈DIGITAL ASSP〉 M66255FP 8192 × 10-BIT LINE MEMORY (FIFO) MITSUBISHI 〈DIGITAL ASSP〉 M66255FP 8192 × 10-BIT LINE MEMORY (FIFO) DESCRIPTION The M66255FP is a high-speed line memory with a FIFO (First In First Out) structure of 8192-word × 10-bit configura- tion which uses high-performance silicon gate CMOS pro- cess technology. It has separate clock, enable and reset signals for write and read, and is most suitable as a buffer memory between de- vices with different data processing throughput. FEATURES • Memory configuration of 8192 words × 10 bits (dynamic memory) • High-speed cycle ............................................. 30ns (Min.) • High-speed access ......................................... 25ns (Max.) • Output hold ........................................................ 5ns (Min.) • Fully independent, asynchronous write and read operations • Variable length delay bit • Output .................................................................... 3 states APPLICATION Digital photocopiers, high-speed facsimile, laser beam print- ers. PIN CONFIGURATION (TOP VIEW) BLOCK DIAGRAM 23 MEMORY ARRAY OF 8192-WORD × 10-BIT CONFIGURATION 22 20 21 WE WRES WCK VCC WRITE ENABLE INPUT WRITE RESET INPUT WRITE CLOCK INPUT 6 7 9 8 RE RRES RCK GND READ ENABLE INPUT READ RESET INPUT READ CLOCK INPUT 16 15 28 INPUT BUFFER DATA INPUT D0 D9 OUTPUT BUFFER 17 18 19 24 25 26 27 1 3 4 5 10 11 12 13 DATA OUTPUT Q0 Q9 DATA INPUT DATA OUTPUT DATA OUTPUT DATA INPUT 28 17 18 19 20 21 22 23 24 25 26 READ ENABLE INPUT WRITE ENABLE INPUT WRITE RESET INPUT WRITE CLOCK INPUT READ RESET INPUT READ CLOCK INPUT 27 1 11 12 15 16 13 14 10 9 8 7 6 5 4 3 2 Q0 ← Q1 ← Q2 ← Q3 ← Q4 ← Q5 ← Q6 ← Q7 ← Q8 ← Q9 ← RCK → RRES → RE → GND ← D0 ← D1 ← D2 ← D3 ← D4 ← WE ← WRES ← WCK ← D5 ← D6 ← D7 ← D8 ← D9 VCC Outline 28P2W-C ~~ 2 14 |
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