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M66257 Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor |
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M66257 Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor |
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2 / 10 page  2 MITSUBISHI 〈DIGITAL ASSP〉 M66257FP 5120 × 8-BIT × 2 LINE MEMORY (FIFO) FUNCTION When write enable input WE is “L”, the contents of data inputs D0 to D7 are written into 1-line delay data only memory in syn- chronization with rise edge of write clock input WCK. At this time, the write address counter of 1-line delay data only memory is also incremented simultaneously. The write functions given below are also performed in syn- chronization with rise edge of WCK. When WE is “H”, a write operation to 1-line delay data only memory is inhibited and the write address counter of 1-line delay data only memory is stopped. When write reset input WRES is “L”, the write address counter of 1-line delay data only memory is initialized. When read enable input RE is “L”, the contents of 1-line delay data only memory are output to data outputs Q00 to Q07 and those of 2-line delay data only memory to data outputs Q10 to Q17 in synchronization with the rise of read clock input RCK. At this time, the read address counters of 1-line and 2-line delay data only memories is also incremented simulta- neously. Moreover, data of Q00 to Q07 are written into 2-line delay data only memory in synchronization with rise edge of RCK. At this time, the write address of 2-line delay data only memory is incremented. The read functions given below are also performed in syn- chronization with rise edge of RCK. When RE is “H”, a read operation from both of 1-line delay data only memory and 2-line delay data only memory is inhib- ited and the read address counter of each memory is stopped. The outputs of Q00 to Q07 and Q10 to Q17 are in the high impedance state. Moreover, a write operation to 2-line delay data only memory is inhibited and the write address counter of 2-line delay data only memory is stopped. When read reset input RRES is “L”, the read address counter of 1-line delay data only memory, and the write address counter and read address counter of 2-line delay data only memory are initialized. |
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