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M66280FP Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor

Part # M66280FP
Description  5120 x 8-BIT LINE MEMORY
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

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5120 x 8-BIT LINE MEMORY
M66280FP
MITSUBISHI <DIGITAL ASSP>
DESCRIPTION
The M66280FP is high speed line memory that uses high
performance silicon gate CMOS process technology and adopts
the FIFO (First In First Out) structure consisting of 5120 words x 8
bits.
The M66280FP, performing reading and writing operations at
different cycles independently and asynchronously, is optimal for
buffer memory to be used between equipment of different data
processing speeds.
FEATURES
• Memory configuration
5120 words x 8 bits (dynamic memory)
• High speed cycle
25 ns (Min.)
• High speed access
18 ns (Max.)
• Output hold
3 ns (Min.)
• Reading and writing operations can be completely carried out
independently and asynchronously.
• Variable length delay bit
• Input/output
TTL direct connection allowable
• Output
3 states
APPLICATION
• Digital copying machine, laser beam printer, high speed facsimile,
etc.
FUNCTION
When write enable input WEB is set to "L", the contents of data
inputs D0 to D7 are read in synchronization with a rising edge of
write lock input WCK to perform writing operation. When this is the
case,the write address counter is also incremented simultaneously.
When WEB is set to "H", the writing operation is inhibited and the
write address counter stops.
When write reset input WRESB is set to "L", the write address
counter is initialized.
When read enable input REB is set to "L", the contents of memory
are output to data outputs Q0 to Q7 in synchronization with a rising
edge of read clock input RCK to perform reading operation. When
this is the case, the read address counter is incremented
simultaneously.
When REB is set to "H", the reading operation is inhibited and the
read address counter stops.
The outputs are placed in a high
impedance state.
When read reset input RRESB is set to "L", the read address
counter is initialized.
PIN CONFIGURATION (TOP VIEW)
Outline 24P2Q-A(SSOP)
24
21
22
23
1
4
3
2
20
5
19
6
16
9
15
10
14
11
13
12
7
8
18
17
Q3
Q0
Q1
Q2
REB
RRESB
D0
D1
D2
D3
WEB
WRESB
Q5
GND
RCK
Q4
Q6
Q7
VCC
WCK
D4
D5
D6
D7
DATA OUTPUT
READ ENABLE
INPUT
READ RESET
INPUT
READ CLOCK
INPUT
DATA OUTPUT
DATA INPUT
WRITE ENABLE
INPUT
WRITE RESET
INPUT
WRITE CLOCK
INPUT
DATA INPUT
1


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