8192 x 8-BIT LINE MEMORY

M66282FP

MITSUBISHI <DIGITAL ASSP>

Output Qn of n cycle <1>* can be read until the start of reading side n cycle <1> and the start of writing side n cycle <2>* overlap each

other.

• Reading shortest n-cycle write data "n"

(Reading side n-1 cycle starts after the end of writing side n-1 cycle.)

WCK

Dn

RCK

Qn

invalid

(n)

(n)

(n+1)

(n+2)

(n+3)

When the reading side n-1 cycle starts before the end of the writing side n+1 cycle, output Qn of n cycle is made invalid.

In the following diagram, reading operation of n-1 cycle is invalid.

• Reading longest n-cycle write data "n": 1 line delay

(When writing side n-cycle <2>* starts, reading side n cycle <1>* then starts.)

Qn

WCK

Dn

(n-1)<1>*

(n)<1>*

(n)<2>*

(n-1)<2>*

RCK

(n)<1>*

(0)<2>*

(n-1)<1>*

(0)<1>*

(n)<0>*

(n-1)<0>*

n+1 cycle

n cycle

n+3 cycle

n+2 cycle

n-2 cycle

n-1 cycle

n cycle

n cycle <1>*

0 cycle <2>*

n cycle <2>*

0 cycle <1>*

n cycle <1>*

n cycle <0>*

<0>*, <1>* and <2>* indicate value of lines.

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