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LM95235CIMMX Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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LM95235CIMMX Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 25 page Logic Electrical Characteristics (Continued) SMBus Digital Switching Characteristics Unless otherwise noted, these specifications apply for V DD= +3.0 Vdc to +3.6 Vdc, CL (load capacitance) on output lines = 80 pF. Boldface limits apply for T A =TJ =TMIN to TMAX; all other limits TA =TJ = +25˚C, unless otherwise noted. The switching characteristics of the LM95235 fully meet or exceed the published specifications of the SMBus version 2.0. The fol- lowing parameters are the timing relationships between SMBCLK and SMBDAT signals related to the LM95235. They adhere to, but are not necessarily, the SMBus specifications. Symbol Parameter Conditions Typical Limits Units (Note 6) (Note 7) (Limit) f SMB SMBus Clock Frequency 100 10 kHz (max) kHz (min) t LOW SMBus Clock Low Time from V IN(0)max to VIN(0)max 4.7 25 µs (min) ms (max) t HIGH SMBus Clock High Time from V IN(1)min to VIN(1)min 4.0 µs (min) t R,SMB SMBus Rise Time (Note 12) 1 µs (max) t F,SMB SMBus Fall Time (Note 13) 0.3 µs (max) t OF Output Fall Time C L = 400 pF, I O = 3 mA, (Note 13) 250 ns (max) t TIMEOUT SMBDAT and SMBCLK Time Low for Reset of Serial Interface (Note 14) 25 35 ms (min) ms (max) t SU;DAT Data In Setup Time to SMBCLK High 250 ns (min) t HD;DAT Data Out Stable after SMBCLK Low 300 1075 ns (min) ns (max) t HD;STA Start Condition SMBDAT Low to SMBCLK Low (Start condition hold before the first clock falling edge) 100 ns (min) t SU;STO Stop Condition SMBCLK High to SMBDAT Low (Stop Condition Setup) 100 ns (min) t SU;STA SMBus Repeated Start-Condition Setup Time, SMBCLK High to SMBDAT Low 0.6 µs (min) t BUF SMBus Free Time Between Stop and Start Conditions 1.3 µs (min) SMBus Communication 20174909 www.national.com 6 |
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