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M21L216128A
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0
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TRUTH TABLE
MODE
CE
WE
OE
LE
HE
DQ1-DQ8
DQ9-DQ16
POWER
LOW BYTE READ (DQ1-DQ8)
L
H
L
L
H
Q
HIGH-Z
ACTIVE
HIGH BYTE READ (DQ9-DQ16)
L
H
L
H
L
HIGH-Z
Q
ACTIVE
WORD READ (DQ1-DQ16)
L
H
L
L
L
Q
Q
ACTIVE
LOW BYTE WRITE (DQ1-DQ8)
L
L
X
L
H
D
HIGH-Z
ACTIVE
HIGH BYTE WRITE (DQ9-DQ16)
L
L
X
H
L
HIGH-Z
D
ACTIVE
WORD WRITE (DQ1-DQ16)
L
L
X
L
L
D
D
ACTIVE
L
X
X
H
H
HIGH-Z
HIGH-Z
ACTIVE
OUTPUT DISABLE
L
H
H
X
X
HIGH-Z
HIGH-Z
ACTIVE
STANDBY
H
X
X
X
X
HIGH-Z
HIGH-Z
STANBY
AC TEST CONDITIONS
Input plus levels
0V to 3.0V
Input rise and fail times
1.5ns
Input timing reference levels
1.5V
Output reference levels
1.5V
Output load
See Figures 1 and 2
DQ
351
DQ
5pF
Z0 =50
30pF
50
3.3V
317
è
è
è
Vt=1.5V
è
Fig.1 OUTPUT LOAD EQUIVALENT
Fig.2 OUTPUT LOAD EQUIVALENT
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