6 / 14 page
$ %
M21L216128A
Elite Semiconduture Memory Technology Inc
Publication Date : Sep. 2000
Revision : 1.0
6/14
NOTES
1.
All voltages referenced to GND (VSS).
2.
Overshoot : VIH
≤ +6.0V for t≤ tRC /2.
Undershoot : VIL
≤ -2.0V for t≤ tRC /2.
3.
ICC is given without output current. ICC increases with greater output loading and faster cycle times.
4.
This parameter is sampled.
5.
Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted.
6.
Output loading is specified with CL=5pF as in Fig.2. Transition is measured
± 500mV from steady static voltage.
7.
At any give temperature and voltage conditions, tCHZ is less than tCLZ and tWHZ is less than tOW
8.
WE is High for Read cycle.
9.
Device is continuously selected. Chip enable and output enables are held in their active state.
10. Address valid prior to, or coincident with, latest occurring chip enable.
11. tRC=Read Cycle Time.
12. Chip Enable and Write Enable can initiate and terminate a Write cycle.
13. Capacitance derating applies to capacitance different from the load capacitance shown in
Fig. 1.
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
